André DeHon
ABSTRACT
No abstract available.
- 1.Peter Athanas and Harvey F. Silverman. Processor Reconfiguration Through Instruction-Set Metamorphosis. IEEE Computer, 26(3):11-18, March 1993. Google Scholar
Digital Library
- 2.Narasimha B. Bhat. Novel Techniques for High Performance Field Programmable Logic Devices. UCB/ERL M93/80, University of California, Berkeley, November 1993. Google ScholarDigital Library
- 3.Andr~ DeHon. DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, 1994.Google Scholar
- 4.Srinivas Devadas, Hi-Keung Ma,, A.R. Newton, and Alberto Sangiovanni-Vincentelli. MUSTANG: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations. IEEE Transactions on Computer-Aided Design of lntegrated Circuits and Systems, 7(12):1290-1300, December 1988.Google ScholarDigital Library
- 5.Robert Francis. Technology Mapping for Lookup-Table Based Field-Programmable Gate Arrays. PhD thesis, University of Toronto, 1992.Google Scholar
- 6.David Hawley. Advanced PLD Architectures. In Will Moore and Wayne Luk, editors, FPGAs, pages 11-23. Abingdon EE&CS Books, 15 Harcourt Way, Abingdon, OX14 1NV, UK, 1991.Google Scholar
- 7.Chris Jones, John Oswald, Brian Schoner, and John Villasenor. Issues in Wireless Video Coding using Run-timereconfigurable FPGAs. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1995. Google ScholarDigital Library
- 8.Rahul Razdan. PRISC: Programmable Reduced Insn'uction Set Computers. PhD thesis, Harvard Univeristy, May 1994. Google ScholarDigital Library
- 9.R. Rudell and A. Sangiovanni-Vincentelli. Multiple-Valued Minimization for PLA Optimization. IEEE Transactions on Computer-AidedDesign of lntegrated Circuits, 6(5):727-751, September 1987.Google ScholarDigital Library
- 10.Ellen M. Sentovich, Kanwar Jit Singh, Luciano Lavagno, Cho Moon, Rajeev Murgai, Alexander Saldanha, Hamid Savoj, Paul R. Stephan, Robert K. Brayton, and Alberto Sangiovanni- Vincentelli. SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41, University of California, Berkeley, May 1992.Google Scholar
- 11.Edward Tau, Ian Eslick, Derrick Chen, Jeremy Brown, and Andr6 DeHon. A First Generation DPGA Implementation. In Proceedings of the Third Canadian Workshop on Field- Programmable Devices, pages 138-143, May 1995.Google Scholar
- 12.Michael J. Wirthlin and Brad L. Hutchings. A Dynamic Instruction Set Computer. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, April 1995. Google ScholarDigital Library
- 13.Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. The Programmable Logic Data Book, 1989, 1994.Google Scholar
Index Terms
- DPGA utilization and application
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