Luis Guerra e Silva
ABSTRACT
For integrated circuit (IC) fabrication technologies of 45nm and below, the impact of process variability in circuit performance is extremely relevant. Parametric static timing analysis (PSTA) techniques, whereby delays are modeled as affine functions of process parameters, were thus introduced to enable the computation of accurate timing estimates, accounting for process variability. Most often, only variations that occur between fabricated ICs (inter-die) are modeled, as the number of variables necessary to model such effects is manageable. Variations that occur across the same IC (intra-die) are usually neglected, as modeling them can add significant complexity to the model. This paper evaluates the impact of modeling intra-die variations in the context of PSTA and proposes effective techniques for handling them.
- A. Agarwal, D. Blaauw, and V. Zolotov. Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. In Proceedings of ICCAD, pages 900--907, San Jose, CA, November 2003. Google Scholar
Digital Library
- S. Boyd and L. Vandenberghe. Convex Optimization. Cambridge University Press, 2004. Google ScholarDigital Library
- H. Chang and S. Sapatnekar. Statistical Timing Analysis Under Spatial Correlations. IEEE Transactions on CAD, 24:1467--1482, September 2005. Google ScholarDigital Library
- C. E. Clark. The Greatest Finite Set of Random Variables. Operations Research, 9:85--91, 1961.Google ScholarDigital Library
- L. G. e Silva, J. Phillips, and L. M. Silveira. Effective Corner-Based Techniques for Variation-Aware IC Timing Verification. IEEE Transactions on CAD, 29:157--162, January 2010. Google ScholarDigital Library
- S. Onaissi and F. N. Najm. A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. IEEE Transactions on CAD, 27:1291--1304, July 2008. Google ScholarDigital Library
- C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, D. K. Beece, J. Piaget, N. Venkateswaran, and J. G. Hemmett. First-Order Incremental Block-Based Statistical Timing Analysis. IEEE Transactions on CAD, 25(10):2170--2180, October 2006. Google ScholarDigital Library
Index Terms
- Handling intra-die variations in PSTA
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