Jagannath Keshava
ABSTRACT
The challenges of post-silicon validation are continuously increasing, driven by higher levels of integration, increased circuit complexity, and platform performance requirements. The pressure of maintaining aggressive launch schedules and containing an increased cost of validation and debug, require a holistic approach to the entire design and validation process. Post-silicon validation is very diverse, and the work starts well before first silicon is available---for example, emulation, design-for-validation (DFV) features, specialized content development, etc. This will require enhancing pre-tape out validation to have healthier first silicon, developing more standard interfaces to our validation hooks, developing more predictive tools for circuit and platform simulation and post-silicon debug, adding more formal coverage methods, and improving survivability to mitigate in-the-field issues. We view the Electronic Design Automation (EDA) industry as a key enabler to help us bridge the gaps between presilicon and post-silicon validation, and extend the considerable intellectual wealth in pre-silicon tools to the post-silicon validation area.
- Intel Corp. 2003. Intel Platform and Component Validation, http://download.intel.com/design/chipsets/labtour/PVPT_WhitePaper.pdfGoogle Scholar
- Bentley B. and Gray R. 2001. Validating the Pentium®4 Processor. Proceedings of the 38th annual Design Automation Conference, Las Vegas, Nevada, United States: ACM, 2001, pp. 244--248. Google ScholarDigital Library
- Silas, I., Frumkin, I., Hazan, E., Mor, E., and Zobin, G., System-Level Validation of the Intel® Pentium® M Processor, Intel Technology Journal, Vol. 7, Issue 2, May 2003 URL: http://developer.intel.com/technology/itj/index.htmGoogle Scholar
- Gray, R. 2008 Post-Silicon Validation Experience: History, Trends, and Challenges. GSRC Workshop on Post-Si Validation, Anaheim, June 9, 2008.Google Scholar
- Patra, P 2007. On the Cusp of a Validation Wall. Design & Test of Computers, IEEE, 24(2), 193--196. Google ScholarDigital Library
- Keshava, J. 2009 Post-Silicon Validation Challenges. International Test Conference 2009, ITC'09, Nov. 1, 2009Google Scholar
- Tiruvallur K. 2009. Beyond Design...Challenges of IA Platform Productization. International Conference on Computer-Aided Design 2009, Nov. 2009.Google Scholar
- Yerramilli, S, 2006. On the Need for Convergence Between Design Validation and Test. In International Test Conference, 2006, ITC'06, 2006, p 14.Google Scholar
- S. Tasiran and K. Keutzer. Coverage metrics for functional validation of hardware designs. IEEE Design & Test of Computers, 18(7):36--45, Jul/Aug 2001. Google ScholarDigital Library
- Bojan, T., Aguilar Arreola, M., Shlomo, E., and Shachar, T. 2007. Functional coverage measurements and results in post-Silicon validation of Core#8482; 2 Duo family. In Proceedings of the 2007 IEEE international High Level Design Validation and Test Workshop (November 07--09, 2007). HLDVT. IEEE Computer Society, Washington, DC, 145--150. Google ScholarDigital Library
- Nejedlo, J.; Khanna, R.; "Intel® IBIST, the full vision realized," Test Conference, 2009. ITC 2009. International, vol., no., pp. 1--11, 1--6 Nov. 2009 doi: 10.1109/TEST.2009.5355667Google Scholar
- Park, S. and Mitra, S. 2008. IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors," Proceedings of the 45th annual conference on Design automation, Anaheim, California: ACM, 2008, pp. 373--378. Google ScholarDigital Library
- Abramovici, M., "A silicon validation and debug solution with great benefits and low costs," International Test Conference, 2007. ITC 2007. IEEE International, 2007, p. 1.Google Scholar
- E. Anis Daoud and N. Nicolici, "Real-Time Lossless Compression for Silicon Debug," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 9, pp. 1387--1400, Sep 2009. Google ScholarDigital Library
- Park, S. et al. 2009. Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA). Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 28(10), 1545--1558 Google ScholarDigital Library
- H. F. Ko and N. Nicolici, "Algorithms for State Restoration and Trace Signals Selection for Data Acquisition in Silicon Debug," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 2, pp. 285--297, Feb 2009. Google ScholarDigital Library
- Chang K., Bertacco, V. Markov, I, 2005. "Simulation-based bug trace minimization with BMC-based refinement," International Conference on Computer-Aided Design, pp. 1045--1051, Nov 6--10, 2005 Google ScholarDigital Library
- Ho, R. et al. 2009. Post-silicon debug using formal verification waypoints. Design and Validation Conference, 2009, DV Con 2009Google Scholar
- Post-silicon validation challenges: how EDA and academia can help
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