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Performance-constrained worst-case variability minimization of VLSI circuits
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 30th international conference on Design automation table of contents
Dallas, Texas, United States
Pages: 154 - 158  
Year of Publication: 1993
ISBN:0-89791-577-1
Authors
A. Dharchoudhury
S. M. Kang
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 0,   Downloads (12 Months): 8,   Citation Count: 1
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. N. Kackar, "Off-line quality control, parameter design and the Taguchi method," J. of Quality Technology, vol. 17, pp. 176-206, Oct. 1985.
 
2
T. K. Yu, S. M. Kang, I. N. Hajj, and T. N. Trick, "Statistical modeling of VLSI circuit performances," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 1013- 1022, Nov. 1989.
 
3
R. M. Biernacki and M. A. Styblinski, "Statistical circuit design with a dynamic constraint approximation scheme," Proc. IEEE ISCAS, pp. 976-979, 1986. San Jose, CA.
 
4
G. Taguchi, "Off-line and on-line quality control systems," Proc. of International Conference on Quality Control, 1987. Tokyo, Japan.
 
5
M. A. Styblinski and J. C. Zhang, "Circuit performance variability reduction: Principles, problems, and practical solutions," Proc. IEEE ICCAD, pp. 170- 173, Nov. 1991. Santa Clara, CA.
 
6
M. D. McKay, It. J. Beckman, and W. J. Conover, "A comparison of three methods for selecting values of input variables in the analysis of output from a computer code," Technometrics, vol. 21, pp. 239-245, May 1979.
 
7
A. Dharchoudhury , S. M. Kang, An integrated approach to realistic worst-case design optimization of MOS analog circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.704-709, June 08-12, 1992, Anaheim, California, United States
 
8
A. Dharchoudhury and S. M. Kang, "iEDISON3.0: A users' guide," 1992.
 
9
P. E. Gill, W. Murray, M. A. Saunders, and M. H. Wright, User's Guide .for NPSOL, version 4.0. Department of Operations Research, Stanford, California, 1986. Report SOL86-2.

CITED BY
 
Tamal Mukherjee , L. R. Carley , R. A. Rutenbar, Synthesis of manufacturable analog circuits, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.586-593, November 06-10, 1994, San Jose, California, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation


General Terms:
Algorithms, Experimentation, Performance

Collaborative Colleagues:
A. Dharchoudhury: colleagues
S. M. Kang: colleagues

Peer to Peer - Readers of this Article have also read:

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