Sukeshwar Kannan
ABSTRACT
In 3D packages top-die power delivery is a not only limited by back-end of line (technology scaling), but also by the TSV integration scheme, the stacking method and the microbump current-carrying capability. The microbump structure and its electromigration time-to-failure (TTF) rate determine the current carrying capability of each TSV, and this is far lower than the current-carrying capability of a C4 bump. Therefore, the power delivery to the top die(s) needs to be distributed through a network of TSVs that tie into the power grid of the top die. The drawback of such a design is the resistive losses in the BEOL of the bottom-die. In this paper, we highlight these challenges faced by each stacking method, and as a promising solution, we will present the use of a voltage-compensation network with dynamic IR-drop sensors that can be used as part of the power-delivery cell to maintain nominal power delivery during all loading cycles. This can help eliminate the use of off-chip voltage regulator modules.
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- [9]., “Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs”, IEEE Transactions on very Large Scale Integration (VLSI) Systems, vol. 24, pp. 1702–1714, 2016.Google ScholarDigital Library
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Index Terms
- Power delivery in 3D packages: Current crowding effects, dynamic IR drop and compensation network using sensors
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