Concept of Strain-Transfer-Layer and Integration with Graded Silicon–Germanium Source/Drain Stressors for p-Type Field Effect Transistor Performance Enhancement

We report a novel strained Si_0.75Ge_0.25 channel p-type field effect transistor (p-FET) that employs a silicon strain-transfer-layer (STL) buried beneath the channel. At the vertical heterojunction, the compliant silicon strain-transfer-layer, improves the coupling of lattice interactions between the lattice-mismatched SiGe source/drain (S/D) stressors and the channel region. In addition, the lattice interaction between the adjacent S/D stressors and the Si_0.75Ge_0.25 channel induces, yet another source of compressive strain in the channel region. A large lateral compressive strain is obtained in the Si_0.75Ge_0.25 channel region for hole mobility enhancement. Devices with gate length L_G down to 50 nm were fabricated. The strain effects resulted in 84% drive current improvement over unstrained Si channel devices.