Impact of Dynamic Stress on Reliability of Nanoscale n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with SiON Gate Dielectric Operating in a Complementary Metal–Oxide–Semiconductor Inverter at Elevated Temperature

This paper investigates the impact of dynamic stress on the reliability of a nanoscale n-channel metal–oxide–semiconductor field effect transistor (nMOSFET) with a SiON gate dielectric operating in a complementary metal–oxide–semiconductor (CMOS) inverter at an elevated temperature T. Experimental results indicate that the shift of threshold voltage V_th by dynamic stress is much larger than that by various static stresses in short channel nMOSFETs. Under a dynamic stress, the OFF-state stress generated interface traps and unfilled electron traps because of the OFF-state hot carrier effect due to drain induced barrier lowering (DIBL) at high T. Although the subsequent ON-state did not produce any new defects, it filled the electron traps, which increased the V_th abruptly. Consecutive application of OFF- and ON-state stresses caused a buildup of recoverable and permanent electron traps, and interface traps, thereby resulting in the significant increase in V_th. In addition, the dynamic stress degradation was frequency-independent up to 500 kHz and its impact on nMOSFET lifetime depends strongly on gate lengths. These results indicate that OFF-state induced defects are the main cause for dynamic stress degradation and can impose a significant limitation on CMOS device scaling.