Experimental Fabrication of XMOS Transistors Using Lateral Solid-Phase Epitaxy of CVD Silicon Films

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Copyright (c) 1990 The Japan Society of Applied Physics
, , Citation Kenichi Ishii et al 1990 Jpn. J. Appl. Phys. 29 L521 DOI 10.1143/JJAP.29.L521

1347-4065/29/4A/L521

Abstract

Experimental fabrication of an XMOS transistor which has two insulated gates called upper-gate and lower-gate has been performed using lateral solid-phase epitaxy of a-Si film deposited by CVD of SiH4. The fabricated XMOS transistors exhibited no punch-through effect and good controllability of the upper-gate threshold voltage by the voltage applied to the lower-gate. It was found that the measured values of the slopes on the upper-gate threshold voltage control by the lower-gate voltage showed good agreement with the calculated value of the slope derived from a simple capacitance couple model.

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