Skip to main content
SpringerLink
Log in

Data processing in the firmware systems for logic control based on search networks

  • Logical Control
  • Published:
Automation and Remote Control Aims and scope Submit manuscript

Abstract

It was proposed to use the hardware accelerators for analysis and data processing in the systems of logic control on a chip including the interacting processor system, memory, and configurable logic components. The data processing expected execution of operations over the sets of elements each of which can be activated by software and realized in the hardware in parallel networks admitting, if necessary, pipeline processing. New methods of design and use of the sorting and search networks were proposed, and the results of their theoretical and experimental comparison with the existing networks were presented.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Lee, E.A. and Seshia, S.A., Introduction to Embedded Systems: A Cyber-Physical Systems Approach, Berkeley, 2015, 2nd ed.

    Google Scholar 

  2. Jensen, J.C., Lee, E.A., and Seshia, S.A., An Introductory Lab in Embedded and Cyber-Physical Systems, Berkeley, 2015.

    Google Scholar 

  3. Rajkumar, R., Lee, I., Sha, L., et al., Cyber-Physical Systems: The Next Computing Revolution, in Proc. 47th ACM/IEEE Design Automation Conf., Anaheim, California, 2010, pp. 731–736.

    Google Scholar 

  4. Vipin, K., Shreejith, S., Fahmy, S.A., et al., Mapping Time-Critical Safety-Critical Cyber Physical Systems to Hybrid FPGAs, in Proc. 2nd IEEE Int. Conf. on Cyber-Physical Systems, Networks, and Applications, IEEE Computer Society, 2014, pp. 31–36.

    Google Scholar 

  5. Panunzio, M. and Vardanega, T., An Architectural Approach with Separation of Concerns to Address Extra-functional Requirements in the Development of Embedded Real-time Software Systems, J. Syst. Architect., 2014, vol. 60, no. 9, pp. 770–781.

    Article  Google Scholar 

  6. Borangiu, A. and Popescu, D., Digital Signal Processing for Knowledge Based Sonotubometry of Eustachian Tube Function, J. Control Eng. Appl. Inform., 2014, vol. 16, no. 3, pp. 56–64.

    Google Scholar 

  7. Sklyarov, V. and Skliarova, I., Digital Hamming Weight and Distance Analysers for Binary Vectors and Matrices, Int. J. Innovat. Comput., Inform. Control., 2013, vol. 9, no. 12, pp. 4825–4849.

    Google Scholar 

  8. Benmoussa, Y., Boukhobza, J., Senn, E., et al., A Methodology for Performance/Energy Consumption Characterization and Modeling of Video Decoding on Heterogeneous SoC and its Applications, J. Syst. Architect., 2015, vol. 61, pp. 49–70.

    Article  Google Scholar 

  9. Zmaranda, D., Silaghi, H., Gabor, G., et al., Issues on Applying Knowledge-Based Techniques in Real- Time Control Systems, Int. J. Comput., Commun. Control, 2013, vol. 8, no. 1, pp. 166–175.

    Article  Google Scholar 

  10. Sklyarov, V.A., Sintez avtomatov na matrichnykh BIS (Design of Automata on Matrix VLSI) Minsk: Nauka i Tekhnika, 1984.

    Google Scholar 

  11. Sklyarov, V., Hierarchical Finite-State Machines and Their Use for Digital Control, IEEE Trans. VLSI Syst., 1999, vol. 7, no. 2, pp. 222–228.

    Article  Google Scholar 

  12. Sklyarov, V., Reconfigurable Models of Finite State Machines and their Implementation in FPGAs, J. Syst. Architect., 2002, vol. 47, pp. 1043–1064.

    Article  Google Scholar 

  13. Baranov, S.I. and Sklyarov, V.A., Tsifrovye ustroistva na programmiruemykh BIS s matrichnoi strukturoi (Digital Devices on Programmable LSI), Moscow: Radio i Svyaz’, 1986.

    Google Scholar 

  14. Sklyarov, V. and Skliarova, I., Hardware Implementations of Software Programs Based on HFSM Models, Comput. Electr. Eng., 2013, vol. 39, no. 7, pp. 2145–2160.

    Article  Google Scholar 

  15. Santarini, M., Products, Profits Proliferate on Zynq SoC Platforms, XCell, 2014, no. 88, pp. 8–15.

    Google Scholar 

  16. Santarini, M., Xilinx 16nm UltraScale+ Devices Yield 2-5X Performance/Watt Advantage, XCell, 2015, no. 90, pp. 8–15.

    Google Scholar 

  17. Xilinx, Inc., Zynq-7000 All Programmable SoC Technical Reference Manual, 2014, http://www.xilinx.com/ support/documentation/user guides/ug585-Zynq-7000-TR M.pdf.

    Google Scholar 

  18. Silva, J., Sklyarov, V., and Skliarova, I., Comparison of On-chip Communications in Zynq-7000 All Programmable Systems-on-Chip, IEEE Embedded Syst. Lett., 2015, vol. 7, no. 1, pp. 31–34.

    Article  Google Scholar 

  19. Sklyarov, V.A., Microprocessor Device for Control of Industrial Equipment, Autom. Remote Control, 1985, vol. 46, no. 1, pp. 102–105.

    Google Scholar 

  20. Sklyarov, V., Skliarova, I., Silva, J., et al., Hardware/Software Co-design for Programmable Systems-on-Chip, Tallinn: TUT Press, 2014.

    Google Scholar 

  21. Skliarova, I., Sklyarov, V., and Sudnitson, A., Design of FPGA-based Circuits Using Hierarchical Finite State Machines, Tallinn: TUT Press, 2012.

    Google Scholar 

  22. Knuth, D.E., The Art of Computer Programming, vol. 3: Sorting and Searching, Reading: Addison-Wesley, 2011.

    MATH  Google Scholar 

  23. Pedroni, V., Compact Hamming-comparator-based Rank Order Filter for Digital VLSI and FPGA Implementations, in Proc. IEEE Int. Symp. on Circuits and Syst., 2004, vol. 2, pp. 585–588.

    Google Scholar 

  24. Sklyarov, V. and Skliarova, I., Fast Regular Circuits for Network-based Parallel Data Processing, Adv. Electr. Comput. Eng., 2013, vol. 13, no. 4, pp. 47–50.

    Article  Google Scholar 

  25. Teubner, J., Mueller, R., and Alonso, G., Frequent Item Computation on a Chip, IEEE Trans. Knowledge Data Eng., 2011, vol. 23, no. 8, pp. 1–15.

    Article  Google Scholar 

  26. Sklyarov, V., Skliarova, I., Rjabov, A., et al., Zynq-based System for Extracting Sorted Subsets from Large Data Sets, J. Microelectron., Electron. Components Mater., 2015, vol. 45, no. 2, pp. 142–152.

    Google Scholar 

  27. Sklyarov, V. and Skliarova, I., High-performance Implementation of Regular and Easily Scalable Sorting Networks on an FPGA, Microprocessors Microsyst., 2014, vol. 38, no. 5, pp. 470–484.

    Article  Google Scholar 

  28. Mueller, R., Teubner, J., and Alonso, G., Sorting Networks on FPGAs, Int. J. Very Large Data Bases, 2012, vol. 21, no. 1, pp. 1–23.

    Article  Google Scholar 

  29. Bunich, A.L., Ginsberg, K.S., Dobrovidov, A.V., Zatuliveter, Yu.S., Prangishvili, I.V., Smolyaninov, V.V., and Sukhov, E.G., Parallel Computation and Control Problems: A Review, Autom. Remote Control, 2002, vol. 63, no. 12, pp. 1867–1883.

    Article  MathSciNet  MATH  Google Scholar 

  30. Sklyarov, V., Skliarova, I., Barkalov, A., et al., Synthesis and Optimization of FPGA-based Systems, New York: Springer, 2014.

    Book  Google Scholar 

  31. Zakrevskij, A. and Sklyarov, V., The Specification and Design of Parallel Logical Control Devices, in Proc. Int. Conf. on Parallel and Distributed Processing Techniques and Applications, 2000, pp. 1635–1641.

    Google Scholar 

  32. Zakrevskii, A.D., Logicheskii sintez kaskadnykh skhem (Logical Design of the Cascade Circuits), Moscow: Nauka, 1981.

    Google Scholar 

  33. Sklyarov, V., Skliarova, I., Rjabov, A., et al., Fast Matrix Covering in All Programmable Systems-on- Chip, Electron. Electric. Eng., 2014, vol. 20, no. 5, pp. 150–153.

    Google Scholar 

  34. Kipfer, P. and Westermann, R., GPU Gems. Improved GPU Sorting, http://http.developer. nvidia.com/GPUGems2/gpugems2 chapter46.html.

  35. Batcher, K.E., Sorting Networks and Their Applications, in Proc. AFIPS Spring Joint Computer Conf., 1968, pp. 307–314.

    Google Scholar 

  36. Aj-Haj Baddar, S.W. and Batcher, K.E., Designing Sorting Networks. A New Paradigm, New York: Springer, 2011.

    Book  Google Scholar 

  37. Chamberlain, R.D. and Ganesan, N., Sorting on Architecturally Diverse Computer Systems, in Proc. 3rd Int. Workshop on High-Performance Reconfigurable Computing Technology and Appl., 2009, pp. 39–46.

    Google Scholar 

  38. Zuluada, M., Milder, P., and Puschel, M., Computer Generation of Streaming Sorting Networks, in Proc. 49th Design Automation Conf., 2012, pp. 1245–1253.

    Google Scholar 

  39. Sklyarov, V. and Skliarova, I., Design and Implementation of Counting Networks, J. Comput., 2015, vol. 97, no. 6, pp. 557–577.

    MathSciNet  MATH  Google Scholar 

  40. Parhami, B., Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters, IEEE Trans. Circuits Syst. II: Express Briefs., 2009, vol. 56, no. 2, pp. 167–171.

    Article  Google Scholar 

  41. Sklyarov, V., Skliarova, I., and Kabulov, A.V., Finding Most Frequently Repeated Data in the Sorted Arrays, Dokl. Uzbek Akad. Nauk, 2014, no. 4, pp. 16–18.

    Google Scholar 

  42. Sklyarov, V., Skliarova, I., and Neves, A., Modeling and Implementation of Automatic System for Garage Control, in Proc. ICROS-SICE Int. Joint Conf., 2009, pp. 4295–4300.

    Google Scholar 

  43. Sklyarov, V. and Skliarova, I., Modeling, Design, and Implementation of a Priority Buffer for Embedded Systems, in Proc. 7th Asian Control Conf., 2009, pp. 9–14.

    Google Scholar 

  44. Digilent, Inc. ZyBo Reference Manual, http://digilentinc.com/Data/Products/ZYBO/ZYBO RM B V6. pdf. 2014.

  45. Avnet, Inc. ZedBoard (ZynqTM Evaluation and Development) Hardware User’s Guide, Version 2.2, http://www.zedboard.org/sites/default/files/, 2014.

Download references

Author information

Authors and Affiliations

  1. Universidade Aveiro, Instituto di Electrónica et Informática, Aveiro, Portugal

    V. Sklyarov & I. Skliarova

Authors
  1. V. Sklyarov
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. I. Skliarova
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to V. Sklyarov.

Additional information

Original Russian Text © V. Sklyarov, I. Skliarova, 2017, published in Avtomatika i Telemekhanika, 2017, No. 1, pp. 121–136.

This paper was recommended for publication by V.M. Vishnevskii, a member of the Editorial Board

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sklyarov, V., Skliarova, I. Data processing in the firmware systems for logic control based on search networks. Autom Remote Control 78, 100–112 (2017). https://doi.org/10.1134/S0005117917010088

Download citation

  • Received:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1134/S0005117917010088

Key words

Search

Navigation