Silicon Device Scaling to the Sub-10-nm Regime
Meikei Ieong,1*
Bruce Doris,2
Jakub Kedzierski,1
Ken Rim,1
Min Yang1
In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.
1 IBM Semiconductor Research and Development Center, T. J. Watson Research Center, Yorktown Heights, NY 10598, USA.
2 IBM Semiconductor Research and Development Center, Microelectronic Division, Hopewell Junction, NY 12533, USA.
* To whom correspondence should be addressed. E-mail: mkieong{at}us.ibm.com
