A CCD-Based Parallel Analog Processor

J. D. Joseph; P. C.T. Roberts; J. A. Hoschette; B. R. Hanzal; J. C. Schwanebeck

doi:10.1117/12.944668

8 November 1984 A CCD-Based Parallel Analog Processor

J. D. Joseph, P. C.T. Roberts, J. A. Hoschette, B. R. Hanzal, J. C. Schwanebeck

Proceedings Volume 0501, State-of-the-Art Imaging Arrays and Their Applications; (1984) https://doi.org/10.1117/12.944668
Event: 28th Annual Technical Symposium, 1984, San Diego, United States

Abstract

The development of a CCD-based parallel analog processor is described. The singleinstruction, multiple-data (SIMD) architecture allows substantial throughput improvements when compared to conventional serial image processing hardware. The heart of the concept is a single-chip array of analog processing elements interconnected with a two-dimensional CCD shift register network. The same analog operation is performed on all cells simultaneously. The device shows great promise in medium resolution (100 x 100) applications (such as guided weapons and robotics) where it can be directly interfaced with a staring focal plane through bump interconnections.

Citation Download Citation

J. D. Joseph, P. C.T. Roberts, J. A. Hoschette, B. R. Hanzal, and J. C. Schwanebeck "A CCD-Based Parallel Analog Processor", Proc. SPIE 0501, State-of-the-Art Imaging Arrays and Their Applications, (8 November 1984); https://doi.org/10.1117/12.944668

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