Fast optical proximity correction with timing optimization ready standard cells

Yifan Qu; Chun Huat Heng; Arthur Tay; Tong Heng Lee

doi:10.1117/12.916124

14 March 2012 Fast optical proximity correction with timing optimization ready standard cells

Yifan Qu, Chun Huat Heng, Arthur Tay, Tong Heng Lee

Proceedings Volume 8327, Design for Manufacturability through Design-Process Integration VI; 832714 (2012) https://doi.org/10.1117/12.916124
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

Resolution enhancement techniques (RET) such as optical proximity correction (OPC) has become an integral part of the fabrication of integrated circuits to maintain the edge placement integrity of the original circuit design. Conventional OPC schemes are usually shape driven and full chip based, resulting in unpredictability in electrical behavior and huge computational effort. To overcome these drawbacks, a new OPC methodology which is electrically driven and based on cell-wise optimization is proposed. Simulation results when compared to conventional OPC approaches in the literature demonstrate better timing accuracy with reduced mask cost. Depending of the circuit test-set, an average run-time improvement between 3 to 8 times is achieved for circuit size with 100 - 400 cells. Further improvements can be obtained by adopting a hybrid approach by only optimizing the timing performance of critical paths. For the hybrid approach, better timing accuracy can be achieved while incurring little penalty on mask cost.

Citation Download Citation

Yifan Qu, Chun Huat Heng, Arthur Tay, and Tong Heng Lee "Fast optical proximity correction with timing optimization ready standard cells", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832714 (14 March 2012); https://doi.org/10.1117/12.916124

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KEYWORDS

Optical proximity correction

Photomasks

Diffusion

Resolution enhancement technologies

Lithography

Performance modeling

Transistors

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