Design on DDR caching control with ping-pong operation for high-speed data acquisition system with PCI Express interface

Xiaoying Zhu; Yong Zhang; Nan Han

doi:10.1117/12.807448

13 October 2008 Design on DDR caching control with ping-pong operation for high-speed data acquisition system with PCI Express interface

Xiaoying Zhu, Yong Zhang, Nan Han

Author Affiliations +

Proceedings Volume 7129, Seventh International Symposium on Instrumentation and Control Technology: Optoelectronic Technology and Instruments, Control Theory and Automation, and Space Exploration; 712921 (2008) https://doi.org/10.1117/12.807448
Event: Seventh International Symposium on Instrumentation and Control Technology, 2008, Beijing, China

Abstract

Data caching is an indispensable part of high-speed data acquisition system, and it makes an important effect on coordinating the speed of data transfer and data processing. In the article, a data caching controller with ping-pong operation is designed after discussion on the features of data transmission with PCI Express interface. The controller's structure and principle is described, as well as the control logic. Additionally, the controller shows the idea of pipeline, where the command sending and data transfer control are separated on controlling the DDR controllers. The result indicates that the design could be widely used in the seamless caching and high-speed data process system. System efficiency will be improved, and the logic design will be simplified.

Citation Download Citation

Xiaoying Zhu, Yong Zhang, and Nan Han "Design on DDR caching control with ping-pong operation for high-speed data acquisition system with PCI Express interface", Proc. SPIE 7129, Seventh International Symposium on Instrumentation and Control Technology: Optoelectronic Technology and Instruments, Control Theory and Automation, and Space Exploration, 712921 (13 October 2008); https://doi.org/10.1117/12.807448

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