Accelerating run-time reconfiguration on custom computing machines

J.-P. Heron; Roger F. Woods

doi:10.1117/12.325718

2 October 1998 Accelerating run-time reconfiguration on custom computing machines

J.-P. Heron, Roger F. Woods

Proceedings Volume 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII; (1998) https://doi.org/10.1117/12.325718
Event: SPIE's International Symposium on Optical Science, Engineering, and Instrumentation, 1998, San Diego, CA, United States

Abstract

Custom computers comprising of a host processor and FPGAs have been proposed to accelerate computationally complex problems. Whilst the FPGA implementation might be considerably faster than its microprocessor counterpart, this performance acceleration can be degraded by the time to reconfigure the FPGA hardware.This paper demonstrates a technique for developing circuits that can reduce the reconfiguration overhead. Circuits for three basic arithmetic functions multiplication, division and square root have been developed using the Xilinx XC6200 reconfigurable FPGA family. Reconfiguration times have been measured by downloading the designs to the VCC HOTWorks custom computing board. A reduction in reconfiguration time of up to 75 percent has been demonstrated using this design approach.

Citation Download Citation

J.-P. Heron and Roger F. Woods "Accelerating run-time reconfiguration on custom computing machines", Proc. SPIE 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, (2 October 1998); https://doi.org/10.1117/12.325718

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