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Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow
Murgida, M.; Panella, A.; Rana, V.; Santambrogio, M.D.; Sciuto, D.;
Very Large Scale Integration, 2006 IFIP International Conference on
Oct. 2006
Page(s):74
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79
Abstract:
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the functionality carried out by the IP-core according to the application's changing needs while it runs. The Caronte methodology, based on the modular design approach, is a design workflow that allows the creation and the handling of partial dynamic reconfigurable architectures using Xilinx FPGAs. In order to speed up its execution, it is important to succeed in quickly generate the EDK-based systems that the flow requires for the elaboration of the correct partial reconfiguration bitstreams. To achieve this goal, an IP-core generator framework has been developed, it receives as input the VHDL description of the core functionality of a module, automatically produces as output an IP-core suitable to be inserted into an EDK system. This binding can be performed in a faster way than using EDK to re-create each time the entire architecture, exploiting the EDK system creator tool. IP-core generator can be used each time an IP-core has to be created, and not only in a dynamic reconfigurability environment. Several tests are presented to validate the proposed methodology
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