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Accurately modeling speculative instruction fetching in trace-driven simulation
Bhargava, R.; John, L.K.; Matus, F.;
Performance, Computing and Communications Conference, 1999. IPCCC '99. IEEE International
10-12 Feb. 1999
Page(s):65
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71
Abstract:
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challenges. A popular evaluation methodology is trace-driven simulation which provides the advantage of a highly portable simulator that is independent of the constraints of the trace generation system. While developing and maintaining a trace-driven simulator is relatively easier than other alternatives, a primary drawback is the inability to accurately simulate speculative instruction fetching and subsequent execution. Fetching from an incorrect path occurs often in a speculative processor, however it is difficult to capture this information in a trace. This paper investigates a scheme to accurately model instruction fetching within a trace-driven framework. This is accomplished by recreating an approximate copy of the object code segment, which we call resurrected code, using a preliminary pass through the trace. We discuss a fast and memory-efficient method for implementing this resurrected code
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