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On the impact of traffic statistics on quality of service for networks on chip
Santi, S.; Lin, B.; Kocarev, L.; Maggio, G.M.; Rovatti, R.; Setti, G.;
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
23-26 May 2005
Page(s):2349
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2352 Vol. 3
Abstract:
Packet switched networks on chip (NoC) architectures have been proposed as a solution to the global interconnect problem in the nanoscale systems on chip (SoC) design era. An important design consideration for NoC, is silicon cost. Towards the goal of keeping the NoC simple, we pose the following question: under what traffic conditions will quality of service (QoS) be provided without the added complexity of an explicit QoS mechanism? In this paper, we take the first step towards answering this question by empirically analyzing different combinations of traffic patterns and injection processes. Specifically, we analyze the effects of different traffic on latency under two cases: (1) an NoC with no QoS mechanism (i.e. without distinction among different classes of service); and (2) an NoC with the simplest distinction into two classes of service: guaranteed service and best effort.
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