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A low-power, memoryless direct digital frequency synthesizer architecture
Palomaki, K.I.; Nittylahti, J.;
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Volume 2,
25-28 May 2003
Page(s):II-77
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II-80 vol.2
Abstract:
In this paper, a compact, low-power, memoryless direct digital frequency synthesizer architecture based on Taylor series approximation is presented. For improved performance, two reference points are applied to the sine and cosine approximation. The advantages of using two reference points include low power consumption, small design area and improved approximation accuracy. Also, a design example outperforming the area and power consumption of the traditional look-up table approach by 10% is presented. The design size is 10,282 transistors and the average power consumption 8.8 mW at 30 MHz system clock.
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