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Serial Sum-Product Architecture for Low-Density Parity-Check Codes
Ratnayake, R.N.S.; Haratsch, E.F.; Gu-Yeon Wei;
Computer Communications and Networks, 2007. ICCCN 2007. Proceedings of 16th International Conference on
13-16 Aug. 2007
Page(s):154
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158
Abstract:
A serial sum-product architecture for low-density parity-check (LDPC) codes is presented. In the proposed architecture, a standard bit node processing unit computes the bit to check node messages sequentially, while the check node computations are broken up into several steps and computed on the fly. This bit node centric architecture requires considerably less memory compared to other serial architectures, including the check node centric architecture.
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