Sumit Roy
- 1.BuildGates. Ambit Design Systems, Santa Clara, CA, 1998.Google Scholar
- 2.H. Choi and S. H. Hwang. Improving the accuracy of support-set finding method for power estimation of combinational circuits. In Proceedings of the International Symposium on Circuits and Systems, Hongkong, June 1997.Google Scholar
- 3.J. Cong and Y. Ding. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Transactions on Computer Aided Design, 13(1):1-12, Jan. 1994.Google ScholarDigital Library
- 4.A. Ghosh, S. Devadas, K. Keutzer, and J. White. Estimation of average switching activity in combinational and sequential circuits. In Proceedings of the Design Automation Conference, pages 253-259, Anaheim, June 1992. Google ScholarDigital Library
- 5.G. Hasteer, A. Mathur, and P. Banerjee. An efficient assertion checker for combinational properties. In Proceedings of the Design Automation Conference, pages 734-739, Anaheim, CA, June 1997. Google ScholarDigital Library
- 6.S. Imam and M. Pedram. Logic extraction and factofization for low power. In Proceedings of the Design Automation Conference, pages 248--253, San Francisco, CA, June 1995. Google ScholarDigital Library
- 7.B. Kapoor. Improving the accuracy of circuit activity measurement. In Proceedings of the Design Automation Conference, pages 734-739, San Diego, June 1994. Google ScholarDigital Library
- 8.R. Marculescu, D. Marculescu, and M. Pedram. Logic level power estimation considering spatiotemporal correlations. In Proceedings of the International Conference on Computer-Aided Design, pages 294-299, Nov. 1994. Google ScholarDigital Library
- 9.F. Najm. Transition density:a new measure of activity in digital circuits. IEEE Transactions on Computer Aided Design, 12(2):310--323, Feb. 1993.Google ScholarDigital Library
- 10.S. Roy. Low-Power-Driven Synthesis Algorithms for Sequential and Combinational Circuits. PhD thesis, University of Illinois, Urbana-Champaign, IL, 1998. Google ScholarDigital Library
- 11.S. Roy, H. Arts, and P. Banerjee. A low-power logic optimization methodology based on a fast power-driven mapping. In Proceedings of the International Conference on Computer Design, Austin, Texas, Oct. 1998. Google ScholarDigital Library
- 12.S. Roy, H. Arts, and P. Banerjee. PowerShake: A low power driven clustering and factoring methodology for boolean expressions. In Proceedings of the Design Automation and Test in Europe, pages 967-968, Paris, France, Feb. 1998. Google ScholarDigital Library
- 13.E.M. Sentovich, K. j. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL M92/41, Electronics Research Laboratory, University of California, Berkeley, CA, May 1992.Google Scholar
Index Terms
- PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis
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