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A slew-rate controlled output driver with one-cycle tuning time
Young-Ho Kwak; Inhwa Jung; Chulwoo Kim;
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific
21-24 March 2008
Page(s):99
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100
Abstract:
A low-power slew-rate controlled output driver with open loop digital scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1 V/ns to 3.6 V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18 um CMOS process, and the control block consumes 13.7 mW at 1 Gbps.
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