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Automatic state space decomposition for approximate FSM traversal based on circuit analysis
Hyunwoo Cho; Hachtel, G.D.; Macii, E.; Poncino, M.; Somenzi, F.;
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Volume 15,
Issue 12,
Dec. 1996
Page(s):1451
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1464
Abstract:
Exploiting circuit structure is a key issue in the implementation of algorithms for state space decomposition when the target is approximate FSM traversal. Given the gate-level description of a sequential circuit, the information about its structure can be captured by evaluating the affinity between pairs or groups of latches. Two main factors have to be considered in carrying out the structural analysis of a sequential circuit: latch connectivity and latch correlation. The first one takes into account the mutual dependency of each memory element on the others; the second one tells us how related are the functions realized by the logic feeding each latch. In this paper we estimate the affinity of two latches by combining these two factors, and we use this measure to formulate the state space decomposition problem as a graph partitioning problem. We propose an algorithm to automatically determine “good” partitions of the latch set which induce state space decomposition, and we present approximate FSM traversal and logic optimization results for the largest ISCAS'89 sequential benchmarks
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