|
1. |
Miniature 3-D inductors in standard CMOS process
Chih-Chun Tang; Chia-Hsin Wu; Shen-Iuan Liu;
Solid-State Circuits, IEEE Journal of
Volume 37,
Issue 4,
April 2002
Page(s):471
-
480
Abstract:
The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-μm one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency fSR of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Qmax. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced
|
Cart
