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IC design of an adaptive Viterbi decoder
Ming-Hwa Chan; Wen-Ta Lee; Mao-Chao Lin; Liang-Gee Chen;
Consumer Electronics, IEEE Transactions on
Volume 42,
Issue 1,
Feb. 1996
Page(s):52
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62
Abstract:
We implement an integrated circuit (IC) design for a decoder of a 64-state binary convolutional code. The decoder is based on a reduced-state adaptive Viterbi algorithm (VA) for which the decoding speed is faster than the standard VA while the error performance remains almost the same. With the adaptive VA, less bits are needed to store and to calculate the metrics of the decoding trellis and less power dissipation is needed, as compared to the standard VA. The IC design is based on a 0.8 μm CMOS technology. The number of quantization levels in the decoding is Q=8
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