Tailoring potentials by simulation-aided design of gate layouts for spin-qubit applications

Open Access

Tailoring potentials by simulation-aided design of gate layouts for spin-qubit applications

Inga Seidler, Malte Neul, Eugen Kammerloher, Matthias Künne, Andreas Schmidbauer, Laura K. Diebel, Arne Ludwig, Julian Ritzmann, Andreas D. Wieck, Dominique Bougeard, Hendrik Bluhm, and Lars R. Schreiber

Phys. Rev. Applied 20, 044058 – Published 23 October 2023

Abstract

Gate layouts of spin-qubit devices are commonly adapted from previous successful devices. As qubit numbers and device complexity increase, modeling new device layouts and optimizing for yield and performance become necessary. The simulation tools used in the advanced semiconductor industry need to be adapted for smaller structure sizes and electron numbers. Here, we present a general approach to electrostatically modeling new spin-qubit-device layouts, considering gate voltages, heterostructures, doping, reservoirs, and an applied source-drain bias. We identify key challenges in spin-qubit-device design: validating the impact on quantum-dot parameters, considering cross-coupling among gates and reservoirs, and ensuring robustness of the design to fabrication limits. We select a demanding target potential to investigate and optimize examples of gate layouts under these challenges. We verify our model by fabricating two simulated designs and indirectly probing the potential landscape through transport measurements.

Received 18 March 2023
Revised 17 June 2023
Accepted 29 September 2023

DOI:https://doi.org/10.1103/PhysRevApplied.20.044058

Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.

Published by the American Physical Society

Physics Subject Headings (PhySH)

Quantum circuits Quantum gates Quantum information with solid state qubits

Nanotechnology Semiconductors

Finite-element method Thomas–Fermi model Transport techniques

Quantum Information, Science & TechnologyCondensed Matter, Materials & Applied Physics

Authors & Affiliations

Inga Seidler ¹, Malte Neul¹, Eugen Kammerloher¹, Matthias Künne¹, Andreas Schmidbauer², Laura K. Diebel², Arne Ludwig ³, Julian Ritzmann³, Andreas D. Wieck ³, Dominique Bougeard², Hendrik Bluhm ¹, and Lars R. Schreiber ^1,*

¹JARA-FIT Institute for Quantum Information, RWTH Aachen University, Aachen 52074, Germany
²Fakultät für Physik, Universität Regensburg, Regensburg 93040, Germany
³Applied Solid State Physics, Ruhr-Universität Bochum, Bochum 44801, Germany

^*lars.schreiber@physik.rwth-aachen.de

Article Text

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Vol. 20, Iss. 4 — October 2023

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Images

Figure 1
Parameter settings. (a) Targeted coupling of a QD (blue) to source (S) and drain (D) reservoirs. The tunnel couplings are identical, i.e., $T_{S} = T_{D}$ , and the capacitive coupling of the dot to the drain is significantly smaller than that to the source, i.e., $C_{D} ≪ C_{S}$ . (b) Schematic potential matching the requirements in (a). The tunnel coupling and the capacitive decoupling are defined by the potentials in sections I and II, respectively. (c),(d) Parameterization of simulation input for $Si$ / $Si Ge$ and $Ga As$ / $(Al, Ga) As$ heterostructures, respectively.
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Figure 2
Modeled electrostatic potential. (a) Potential realization for a doped $Ga As$ / $(Al, Ga) As$ heterostructure. The gate structure (black) and the pathline section used for visualization (white) are indicated, as well as the sensor QD and DQD regions (dashed orange lines). (b) Line section of potential $V$ (blue) and charge-carrier density $ρ$ (green) along the line section for the realization in (a). The source and drain levels are indicated (black dashed lines). (c) Potential realization for an undoped $Si$ / $Si Ge$ heterostructure with a global top gate. (d) Line section of potential and charge-carrier density along the pathline section used for visualization for the realization in (c). (e) Potential realization for a closed-gate design in an undoped $Si$ / $Si Ge$ heterostructure with the first gate layer (black). (g)–(i) Stacking of layers 1 (yellow), 2 (blue), and 3 (purple) in closed-gate design.
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Figure 3
Experimental variation of the slide region. (a) Scanning electron micrograph (SEM) of an identical device with slide gate (SR), plunger (PS), and sensor-dot Ohmic contacts (crosses) marked. (b),(c) Coulomb diamonds with slope $m$ shown for $V_{SR} = 0.35$ V and $V_{SR} = 0.24$ V, respectively. (d) Coulomb-diamond slope (blue) and $η$ (green) as a function of slide-gate voltage.
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Figure 4
Influence of bias. (a) SEM of an identical device with slide gate (DB5) and sensor plunger (DB2) marked. (b) Simulation of influence of bias on the potential formed. When only the bias voltage is increased, the slide length of the induced potential $V$ (solid lines) increases. Accordingly, the charge density $ρ$ (dashed lines) extends into the slide region, depending on the applied bias. The beginning of the drain reservoir is marked with red arrows. (c) Coulomb diamonds of a symmetrically coupled QD operation with an asymmetrically applied bias voltage. The slopes (white lines) of the Coulomb diamonds are extracted from the dependence on the applied bias. A current level of 1.5 nA is used as a threshold. For clarity, the low-bias regime is depicted as an inset. To realize the symmetric coupling of the reservoirs to the QD operation, the slide-forming gate voltage $V_{DB 5}$ is set to zero. (d) Coulomb diamonds of an asymmetrically coupled QD operation with $V_{DB 5} = - 0.31$ V. For the same current threshold $I = 1.5$ nA, the slopes $m$ (white lines) are extracted. The extracted $m$ for both operation modes is depicted in the inset as a function of the applied bias.
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Figure 5
Robustness of potential. (a) SEM of an identical device. The edges of the fabricated gates (yellow) are extracted by image processing. (b) Potential along line section using the gate edges in (a) of a fabricated device (blue) and optimal gate edges (green). (c) Influence of slide angle on line-section potential. The slide angle is varied by changing the $y$ position of the endpoint of the slide [blue dot in (a)]. The inset shows compensation by tuning of the slide voltage for $Δ y = - 10$ nm. Starting from the top, $Δ V_{SR, i} = (i - 1) \times 10$ mV. (d) Influence of slide angle for a simpler device (layout in inset). (e) Cross section of slide potential and electrical field perpendicular to the path at the position marked in red in (a). The gate edges are marked in orange, and the quantum well (red arrow) is placed at $z = - 45$ nm. (f) Cross section of slide potential and electrical field perpendicular to the path in the simple device at the position marked in red in the inset of (d).
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Figure 6
Determination of the gate lever arm $α_{D}$ by simulation. (a) Potential along line sections for various bias voltages $V_{SD}$ . (b) Change in potential minimum $Δ V_{dot}$ , obtained from an interpolation in the QD region of the 2D data for the line sections of the potential in (a), as a function of the change in bias voltage $Δ V_{SD}$ . The data points are linearly fitted to obtain the slope $α_{D}$ (green).
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