Two-dimensional (2D) semiconductors, e.g., $\mathrm{Mo}{\mathrm{S}}_2$ and phosphorene, are promising candidates for the channel materials of next-generation field-effect transistors (FETs). Although 2D $\mathrm{Mo}{\mathrm{S}}_2$ FETs with the gate length $L_g$ scaled down to 1 nm have been fabricated with a quite small threshold swing, they suffer from a rather low ON current and are unsuitable for a high-performance device. Herein, we simulate sub-5-nm monolayer (ML) phosphorene MOSFETs using ab initio quantum-transport simulations. We predict that the ON current, delay time, and power dissipation indicator of the sub-5-nm double-gated ML phosphorene MOSFETs with proper underlap structure can fulfill the requirements of the international technology roadmap for semiconductors for both high-performance (along both the armchair and zigzag directions) and low-power (along the zigzag direction) devices in 2028 until $L_g$ is scaled down to 2 nm. Therefore, phosphorene is more suitable for ultrascaled FETs than 2D $\mathrm{Mo}{\mathrm{S}}_2$ in the post-silicon era as far as the ON current is concerned.

• Received 22 March 2018
• Revised 29 June 2018

DOI:https://doi.org/10.1103/PhysRevApplied.10.024022