Summary
|
For Full-Text PDF, please login, if you are a member of IEICE, or go to Pay Per View on menu list, if you are a nonmember of IEICE. |
|
Experimental Study of Jitter Effect on Digital Downconversion Receiver with Undersampling Scheme Minseok KIM Aiko KIYONO Koichi ICHIGE Hiroyuki ARAI Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.7 pp.1430-1436 Publication Date: 2005/07/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.7.1430 Print ISSN: 0916-8532 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Communications and Wireless Systems Keyword: clock jitter, undersampling, downconversion, DDC, EVM, Full Text: PDF(503.8KB)>>
Summary: Undersampling (or bandpass sampling) phase modulated signals directly at high frequency band, the harmful effects of the aperture jitter characteristics of ADCs (Analog-to-Digital converters) and sampling clock instability of the system can not be ignored. In communication systems the sampling jitter brings additional phase noise to the constellation pattern besides thermal noise, thus the BER (bit error rate) performance will be degraded. This paper examines the relationship between the input frequency to ADC and the sampling jitter in digital IF (Intermediate Frequency) downconversion receivers with undersampling scheme. This paper presents the measurement results with a real hardware prototype system as well as the computer simulation results with a theoretically modeled IF sampling receiver. We evaluated EVM (Error Vector Magnitude) in various clock jitter configurations with commonly used and reasonable cost ADCs of which sampling rates was 40 MHz. According to the results, the IF input frequencies of QPSK (16 QAM) signals were limited below around 290 (210) MHz for wireless LAN standard, and 730 (450) MHz for W-CDMA standard, respectively, in our best configuration. | ||||||||||
| ||||||||||
