Skip Navigation

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2007 E90-A(5):1028-1037; doi:10.1093/ietfec/e90-a.5.1028
This Article
Right arrow Full Text (PDF)
Right arrow References
Right arrow Alert me when this article is cited
Right arrow Alert me if a correction is posted
Services
Right arrow Email this article to a friend
Right arrow Similar articles in this journal
Right arrow Alert me to new issues of the journal
Right arrow Add to My Personal Archive
Right arrow Download to citation manager
Right arrow Request Permissions
Google Scholar
Right arrow Articles by WANG, Y.
Right arrow Articles by ZOU, Y.
Right arrow Search for Related Content
Social Bookmarking
 Add to CiteULike   Add to Connotea   Add to Del.icio.us  
What's this?

Copyright © 2007 The Institute of Electronics, Information and Communication Engineers

Regular Section -- Papers -- VLSI Design Technology and CAD

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration*

Yibo WANG1, Yici CAI1, Xianlong HONG1 and Yi ZOU1

1 The authors are with the Department of Computer Science and Technology, Tsinghua University, Beijing, China. E-mail: wangyibo{at}mails.tsinghua.edu.cn, E-mail: caiyc{at}tsinghua.edu.cn, E-mail: hxl-dcs{at}tsinghua.edu.cn, E-mail: zou_yi00{at}mails.tsinghua.edu.cn


   Abstract

Buffer insertion plays a great role in modern global interconnect optimization. But too many buffers exhaust routing resources, and result in the rise of the power dissipation. Unfortunately, simplified delay models used by most of the present buffer insertion algorithms may introduce redundant buffers due to the delay estimation errors, whereas accurate delay models expand the solution space significantly, resulting in unacceptable runtime. Moreover, the power dissipation problem becomes a dominant factor in the state-of-the-art IC design. Not only transistor but also interconnect should be taken into consideration in the power calculation, which makes us have to use an accurate power model to calculate the total power dissipation. In this paper, we present two stochastic optimization methods, simulated annealing and solution space smoothing, which use accurate delay and power models to construct buffered routing trees with considerations of buffer/wire sizing, routing obstacles and delay and power optimization. Experimental results show our methods can save much of the buffer area and the power dissipation with better solutions, and for the cases with pins ≤ 15, the runtime of solution space smoothing is tens of times faster.

Key Words: interconnect optimization, accurate delay model, low power, buffer insertion


Manuscript received May 15, 2006. Manuscript revised December 2, 2006. Final manuscript received February 2, 2007.

* This paper is supported by the National Science Foundation of China (NSFC) 60476014.


Add to CiteULike CiteULike   Add to Connotea Connotea   Add to Del.icio.us Del.icio.us    What's this?




Disclaimer:
Please note that abstracts for content published before 1996 were created through digital scanning and may therefore not exactly replicate the text of the original print issues. All efforts have been made to ensure accuracy, but the Publisher will not be held responsible for any remaining inaccuracies. If you require any further clarification, please contact our Customer Services Department.