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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 2005 E88-A(4):869-875; doi:10.1093/ietfec/e88-a.4.869
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Copyright © 2005 The Institute of Electronics, Information and Communication Engineers

Bitwidth Optimization for Low Power Digital FIR Filter Design

Kosuke TARUMI1, Akihiko HYODO1,3, Masanori MUROYAMA1 and Hiroto YASUURA1,2

1 The authors are with the Graduate School of Information Science & Electrical Engineering, Kyushu University, Kasuga-shi, 816-8580 Japan. E-mail: tarumi{at}c.csce.kyushu-u.ac.jp, 2 The author is with the System LSI Research Center, Kyushu University, Kasuga-shi, 816-8580 Japan., 3 Presently, with Central Research Laboratory, Hitachi, Ltd.

We propose a novel approach for designing a low power datapath in wireless communication systems. Especially, we focus on the digital FIR filter. Our proposed approach can reduce the power consumption and the circuit area of the digital FIR filter by optimizing the bitwidth of the each filter coefficient with keeping the filter calculation accuracy. At first, we formulate the constraints about keeping accuracy of the filter calculations. We define the problem to find the optimized bitwidth of each filter coefficient. Our defined problem can be solved by using the commercial optimization tool. We evaluate the effects of consuming power reduction by comparing the digital FIR filters designed in the same bitwidth of all coefficients. We confirm that our approach is effective for a low power digital FIR filter.

Key Words: low power design, bitwidth optimization, digital FIR filter

Manuscript received June 25, 2004. Manuscript revised October 6, 2004. Final manuscript received December 6, 2004.


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