|
For Full-Text PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
|
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation
Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI
Publication
IEICE TRANSACTIONS on Electronics
Vol.E89-C
No.11
pp.1526-1534 Publication Date: 2006/11/01 Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.11.1526 Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: SRAM, cell terminal biasing, differential cell terminal, SNM, write margin, disturb,
Full Text: PDF(7.4MB)>>
Summary:
Fundamental limitation on assisting a write margin (WRTM) by reducing the cell terminal bias (VDDM) has been made clear for the first time and the new cell terminal biasing scheme featuring a differential VDDM (Diff-VDDM) control has been proposed to address the issues which the conventional schemes proposed so far can not overcome [1]-[5]. Since Diff-VDDM biasing scheme can meet the both of the requirements simultaneously of 1) reducing drivability for the PMOS load transistor on the "Low" written bit-line (BL) side, and 2) increasing drivability for the other side PMOS for a write recovery, it can provide a lower minimum operating voltage (Vdd_min) for the write operation even if considering a sufficiently-large random threshold voltage (Vth) variations. The following points have been shown based on an actual 65 nm CMOS device variation data and the implemented layout data that 1) Vdd_min for the write operation can be lowered from Vdd=1.1 V down to 0.8 V when considering a 4-sigma (σ) variation, 2) the write recovery time can be reduced by 92% and 70% that for the conventional schemes [1],[2] at Vdd=0.7 V and 1.0 V, respectively, and 3) WRTM defined by the percentage (%) of the required (BL pull-down level/Vdd) to flip the cell nodes for the write operation can be relaxed by 2.6-fold and 1.4-fold that for the conventional schemes [1],[2] at Vdd=0.75 V and 1.0 V, respectively. As an actual implementation in a 65 nm CMOS, a 32-kbit single-port SRAM macro design and the measured butterfly curves have been demonstrated.
|
|
|