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IEICE Transactions on Electronics 2005 E88-C(4):656-661; doi:10.1093/ietele/e88-c.4.656
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Copyright © 2005 The Institute of Electronics, Information and Communication Engineers

Separation by Bonding Si Islands (SBSI) for Advanced CMOS LSI Applications

Takashi YAMAZAKI1, Shun-ichiro OHMI1, Shinya MORITA1, Hiroyuki OHRI1, Junichi MUROTA2, Masao SAKURABA2, Hiroo OMI3 and Tetsushi SAKAI1

1 The authors are with Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama-shi, 226-8502 Japan. E-mail: takashi.yamazaki{at}lsi.ip.titech.ac.jp, 2 The authors are with Research Institute for Electrical Communications, Tohoku University, Sendai-shi, 980-8577 Japan., 3 The author is with NTT Basic Research Laboratories, NTT Corporation, Atsugi-shi, 243-0198 Japan.

We have developed separation by bonding Si islands (SBSI) process for advanced CMOS LSI applications. In this process, the Si islands that become the SOI regions are formed by selective etching of the SiGe layer in the Si/SiGe stacked layers, and those are bonded to the Si substrate with the thermal oxide layers by furnace annealing. The etching selectivity for SiGe/Si and surface roughness after the SiGe etching were found to be improved by decreasing the HNO3 concentration in the etching solution. The thicknesses of the fabricated Si island and the buried oxide layer also became uniform by decreasing the HNO3 concentration. In addition, it was found that the space formed by SiGe etching in the Si/SiGe stacked layers was able to be filled with the thermal oxide layer without furnace annealing.

Key Words: silicon on insulator (SOI) wafer, patterned SOI, SiGe, selective etching, MOSFET

Manuscript received September 6, 2004. Manuscript revised October 26, 2004.


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