Influence of bank geometry on the electrical characteristics of printed organic field-effect transistors

Organic field-effect transistors (OFETs) are of great interest in research and industry for the realization of flexible electronic devices due to their low-cost manufacturing, mechanical flexibility, lightweight and large-area processability. In particular, solution processes such as spin-coating [1], casting [2, 3], shearing [4, 5], and printing are strongly desired to fully exploit the advantages of OFETs [6, 7]. Among them, printing is considered as a promising candidate due to additive process, maskless patterning, and low waste. The electrical performance of printed devices has been remarkably enhanced by adopting new device structures [8, 9], optimizing printing processes [10], and improving crystallinity of the organic semiconductor (OSC) layers for the realization of practical electronic applications [11, 12]. In addition, the uniformity of OFETs has been improved by blending polymer insulators [13–15], tuning surface conditions [16], and reducing fabrication factors [17].

There have been many successful attempts with solution-processable 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) as the active channel material in OFETs. TIPS-pentacene, one of the most widely used small-molecule OSCs, has been successfully reported for high uniformity and field-effect mobility (μ_FET) by tuning the crystallinity, crystal orientation, and molecular packing of OSC thin films. The higher mobility is generally achieved when the OSC crystals are larger and well aligned along the direction of charge transport by controlling the direction and degree of crystallization over a device area [18, 19]. Yang et al reported a pneumatic nozzle printing technique to control the crystal growth of TIPS-pentacene thin films [10]. They controlled the size and orientation of crystalline domain by tuning the substrate temperature and printing speed. Bao and coworkers have achieved patterned and aligned single-crystalline TIPS-pentacene thin films while maintaining non-equilibrium molecular packing motifs by fluid flow engineering [18]. They also demonstrated the growth of strained lattice and aligned crystals of TIPS-pentacene thin films by laterally confining the OSC crystal growth during solution shearing [19]. By combining the surface wetting properties and solution shearing, TIPS-pentacene crystalline domains were effectively patterned and aligned in a single step [20]. Xiao et al conveniently patterned TIPS-pentacene single-crystalline arrays by combining the space-restricted and field/force-induced strategies [21]. However, most of these techniques require complicated processes and specialized fabrication due to extra steps such as photolithography processes and/or selective surface treatments.

In this work, we introduce a simple strategy that efficiently improved the device performance and uniformity by using a pneumatic nozzle printing technique. The banks of Cytop were used to concentrate the OSC ink into defined areas by forming microwells, resulting in a uniform film morphology. We control the crystal size and crystalline domain orientation of TIPS-pentacene thin films by modifying the bank dimension in which OSC inks are printed. The electrical characteristics of OFETs, including uniformity, with various bank geometries were measured to investigate the effect of TIPS-pentacene thin film crystalline domain sizes and directions on the device performance. The morphology of TIPS-pentacene thin films was evaluated by determining the orientation and degree of crystalline domains. The OFET with the optimized bank geometry, resulting in well-aligned crystalline domains along the charge transport direction, exhibited a field-effect mobility of 0.23 cm² V⁻¹ s⁻¹ and a relative standard deviation (RSD) of 16%, which was four-fold increase and one third decrease, respectively, compared with other bank geometries. This work provides a step forward to develop practical electronic applications with high device performance and uniformity while maintaining an easy and simple fabrication process.

2.1. Device fabrication

2.2. Characterization

Figure 1(a) illustrates the fabrication processes for the printed OFET based on TIPS-pentacene (see supplementary movies 1 and 2 is available online at stacks.iop.org/FPE/4/042001/mmedia). After the deposition of the gate electrode and dielectric layers, Cytop solution was printed on the gate dielectric using a pneumatic nozzle printer to form the bank patterns, followed by the OSC solution printing in the defined area by bank patterns. The Cytop banks were hydrophobic, whereas the inner surface was hydrophilic, to prevent droplets pinning at the bank walls and ensure that the TIPS-pentacene inks were filled uniformly and evaporated slowly. To control the crystalline domains of the TIPS-pentacene thin films, we fabricated bank patterns in three different dimensions; the length and width of banks I, II, and III were 1830 μm × 1120 μm, 3660 μm × 1120 μm, and 1830 μm × 2240 μm, respectively (figures 1(b)–(d) and S1). Bank I, the reference pattern herein, was the most desired dimension because it requires the smallest occupied area and least material consumption. A TIPS-pentacene thin film printed in bank I shows a radial crystalline domain as shown in figure S2(a). Under bank II, the extended length pattern, the crystalline domains of TIPS-pentacene thin films were more aligned in a parallel manner with respect to the bank I pattern, which were perpendicular to the charge transport direction (figure S2(b)). Meanwhile, more perpendicularly aligned crystalline domains of TIPS-pentacene thin films with respect to the bank I pattern were observed under bank III, the extended width pattern (figure S2(c)).

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The electrical characteristics were measured to investigate the effects of bank patterns on the device performance (figure 2). To verify only the effects of bank patterns, we deposited the gate dielectric and OSC layers at the same time. The transfer characteristics represented in terms of the drain-source current (I_DS) as a function of the gate-source voltage (V_GS) were considerably dependent on the bank types (figure 2(a)). The OFET under bank III exhibited two times higher I_DS than that under banks I and II. However, the gate-source current (I_GS) was measured in the range of 10⁻¹² to 10⁻¹⁰ A due to the reliable Parylene copolymer gate dielectric bulk quality [22]. The transfer curves show a negligible hysteresis behavior within the forward and reverse V_GS scans, regardless of bank patterns. To quantitatively compare the device performance, the electrical parameters such as threshold voltage (V_TH), μ_FET, and on/off current ratio (I_on/I_off) were extracted using the following equation:

$$\begin{eqnarray*}&&{I}_{{\rm{DS}}}=\displaystyle \frac{{W}_{{\rm{CH}}}}{2{L}_{{\rm{CH}}}}{\mu }_{{\rm{FET}}}{C}_{{\rm{OX}}}{({V}_{{\rm{GS}}}-{V}_{{\rm{TH}}})}^{2},\end{eqnarray*}$$

where C_OX is the gate dielectric capacitance per unit area and W_CH and L_CH are the channel width and length, respectively. The extracted dielectric constant and estimated dielectric thickness were 3.15 at 10 Hz and 200 nm, respectively (figure S3). The extracted V_TH was about −1.24 V, regardless of bank type, because the same device structure was employed for the fabrication of OFETs. On the other hand, other parameters such as μ_FET and I_on/I_off varied slightly with the bank patterns. The OFET under bank III exhibited the highest μ_FET of 0.22 cm² V⁻¹ s⁻¹ compared to those under banks I and II, which showed μ_FET values of 0.05 and 0.06 cm² V⁻¹ s⁻¹, respectively. An I_on/I_off higher than 10⁵ was obtained from the OFET under bank III while OFETs under banks I and II showed a half order of magnitude decrease of I_on/I_off. To optimize the bank dimensions, we further extended the bank width by four times, namely banks IIIa and IIIb. Despite longer length of the bank patterns, OFETs show negligible changes in terms of the V_TH, μ_FET, and I_on/I_off compared to bank III. The output characteristics supported the observations that the device performance was considerably dependent on the bank patterns (figure 2(b)). The output curves show good saturation behaviors and no sign of significant contact resistance issues, regardless of bank type. The results indicated that bank III improves the device performance, resulting in four times enhancement of μ_FET and two times higher I_on/I_off, without additional fabrication processes for OSC deposition such as contact and interfacial engineering. The electrical parameters are summarized in table 1.

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From the electrical results, we observed the correlation between TIPS-pentacene thin film crystalline degree and device performance (figure 3). The 2D-GIXRD analysis provided that the crystal structure of the TIPS-pentacene thin film was identical, regardless of bank pattern (figures 3(a)–(c)). The diffraction spectra under different bank patterns show (00l) reflections corresponding to a q_z axis with an interlayer distance (d-spacing, d = 2πq_r,z⁻¹) of 17.1 Å, which indicated that the molecular structure was perpendicular to the substrate (figure 3(d)). It is noted that the charge transport was hindered by the coexistence of the two different crystalline phases of small-molecule OSCs, inducing the charge carrier trap sites [23, 24]. The crystalline degree of the TIPS-pentacene thin films along to charge transport direction was determined using POM images (figures 3(e)–(g)). The crystalline domains show radial, parallel, and perpendicular respect to the charge transport direction under banks I, II, and III, respectively. Figure S4 and table S1 show a method for estimating the crystalline degree of TIPS-pentacene thin films from a POM images. The crystalline degree was averaged from ten channels for each bank pattern and summarized in table S2. Under bank III, the TIPS-pentacene thin film exhibited the highest crystalline degree of 51° (figure 3(h)). In addition, the crystalline degree was maintained for the extended width bank pattern. In contrast, the 27° and 32° of the crystalline domains were observed under banks I and II, respectively. This can be attributed to drying solvents from the center radially outward bank patterns.

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The uniformity, one of the most important issues before commercialization, was determined by calculating the RSD of μ_FET. Despite a similar crystalline degree, the TIPS-pentacene thin film printed in bank I showed various crystalline degrees, resulting in high RSD of field-effect mobility. Under bank II, the crystalline domains of the TIPS-pentacene thin film were grown in a perpendicular direction respect to the charge transport, but larger and similar degrees of crystalline domains led to relatively low RSD compared to the OFET using bank I. The results indicated that bank III led to a higher and more oriented crystalline domain along the charge transport direction, which allows the isotropy of charge transport. The RSD was remarkably decreased from 50% to 16% by employing bank III. In other words, the crystalline domain in the same direction of the charge transport improves the uniformity and device performance simultaneously by reducing the trap states at the grain boundaries. The difference in field-effect mobility under different bank dimensions can be attributed to the difference in the degree of crystallinity of TIPS-pentacene thin films. In addition, bank III contains a lower density of grain boundaries, resulting in higher field-effect mobility. Furthermore, since the crystalline domains are aligned along the charge transport, field-effect mobility is likely further enhanced. Therefore, we concluded that the crystalline degree of TIPS-pentacene respect to the contact electrodes is the major factor that bring the higher device performance.

The fundamental parameters of OFETs based on TIPS-pentacene fabricated in various techniques were summarized in table 2 in terms of the number of extra processes for OSC deposition, OSC preparation, operation voltage, channel dimensions, field-effect mobility in the saturation regime, and RSD. We efficiently improved the device performance using only bank printing without complicated manufacturing processes. By comparing with previously published papers, the 0.22 cm² V⁻¹ s⁻¹ of field-effect mobility is comparable or relatively low, but the operating voltage is only 10 V, and the RSD decreased to only 16%.

In conclusion, we have efficiently improved the device performance using a simple printing process, which added only one more step for OSC deposition. By tuning the bank pattern, we were able to control the degree of crystalline domains of TIPS-pentacene thin films. Under the optimized bank dimension, bank III, a TIPS-pentacene thin film exhibits a well-oriented crystalline domain along the charge transport direction, resulting in the highest μ_FET of 0.22 cm² V⁻¹ s⁻¹ and lowest RSD of 16%, compared to OFETs using banks I and II. We observed the correlation between the degree of crystalline domains and device performance including the field-effect mobility and uniformity. Since the device structure and materials for OFETs were exactly the same, other parameters such as V_TH, contact resistance, and crystal structure of OSCs were almost identical, regardless of bank patterns. As a result, a solution-processed low-voltage OFET was successfully demonstrated in printing techniques and the device performance was considerably enhanced by tuning the bank dimensions, resulting of charge transport enhancement. This work provides an approach to the development of practical electronic devices in simple and low-cost manufacturing systems with high uniformity.

This work was supported by grants (Code No. CASE-2016R1E1A2020535 and CASE-2015M3A6A5065315) from the Center for Advanced Soft Electronics under the Global Frontier Research Program of the Ministry of Science and ICT of South Korea, and by the IT Consilience Creative Program (IITP-2019-R0346-15-1007) supervised by IITP (Institute for Information & Communications Technology Promotion).