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Reduction of channel resistance in amorphous oxide thin-film transistors with buried layer

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Published under licence by IOP Publishing Ltd
, , Citation Eugene Chong et al 2012 IOP Conf. Ser.: Mater. Sci. Eng. 34 012005 DOI 10.1088/1757-899X/34/1/012005

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1 Electronic Materials Research Center, Korea Institute of Science and Technology (KIST), Seoul, 136-791, Republic of Korea

2 Nanomaterials Science and Engineering, University of Science and Technology (UST), Daejeon, 305-333, Republic of Korea

3 Convergence Components & Materials Research Laboratory, Electronics and Telecommunications Research Institute (ETRI), Deajeon 305-700, Republic of Korea

4 Department of Semiconductor Engineering, Cheongju University, Cheongju, Chungbuk, 360-764, Republic of Korea

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1757-899X/34/1/012005

Abstract

A silicon-indium-zinc-oxide (SIZO) thin film transistor (TFT) with low channel-resistance (RCH) indium-zinc-oxide (In2O3:ZnO = 9:1) buried layer annealed at low temperature of 200°C exhibited high field-effect mobility (μFE) over 55.8 cm2/V·s which is 5 times higher than that of the conventional TFTs due to small threshold voltage (Vth) change of 1.8 V under bias-temperature stress (BTS) condition for 420 minutes. The low-RCH buried-layer allows more strong current-path formed in channel layer well within relatively high-RCH channel-layer since it is less affected by the channel bulk and/or back interface trap with high carrier concentration.

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10.1088/1757-899X/34/1/012005