A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

A gated ring oscillator (GRO) based time-to-digital converter (TDC) is presented. To enhance the resolution of the TDC, a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2. The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm². According to the measurement results, the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range, the maximum clock frequency of this circuit is larger than 200 MHz. Under a 1 V power supply, with a 200–800 ps input time difference, the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.