Improvement of SiN_x:H/InP gate structures for the fabrication of metal–insulator–semiconductor field-effect transistors

In this paper we report on the optimization of the SiN_x:H insulator, deposited by the electron cyclotron resonance (ECR) plasma method, as a dielectric for metal–insulator–semiconductor (MIS) structures built on an InP compound semiconductor. Two different MIS structures have been obtained in which the minimum of the interface trap density (D_it,min) at the insulator/InP interface attains values of device quality. In the first structure, a Al/SiN_1.5:H/SiN_1.6:H/InP dual-layer insulator was obtained and optimized after rapid thermal annealing treatment at 500 °C for 30 s. After this treatment, the value of D_it,min was 9 × 10¹¹ cm⁻² eV⁻¹. In the second structure, the MIS structure was Al/SiN_1.6:H/InP single-layer insulator, in which the InP surface was exposed to an N₂ plasma prior to the SiN_1.6:H film deposition. In this case, the value of D_it,min was 1.6 × 10¹² cm⁻² eV⁻¹. Both types of structures were used as gate insulators on N-channel enhanced-mode MIS field-effect transistor test devices. From the dc output characteristics of the transistors, we obtain values for the electron channel mobility in the range 1550–1600 cm² V⁻¹ s⁻¹. This is a confirmation of the great potential of the ECR plasma method as a simple way to obtain device quality gate structures on InP without the use of passivation processes of the InP surface prior to the deposition of the gate dielectric, thus simplifying the whole device fabrication procedure.