The author describes the parallelisation of three different versions of the CCITT H.261 encoder algorithm using a generalised parallel design methodology based upon pipelines of processor farms (PPFs). For each algorithm, a theoretical upper-bound scaling model was derived by analysing the execution time profile of the algorithm and its feedback structure. The performance predicted by the model was, in each case, in good agreement with that achieved by the corresponding practical implementation. Practical throughput scaling up to a factor of 11 was achieved, using PPFs containing up to 16 processors. The design examples illustrate the impact which feedback has on potential speedup for image coding algorithms, and the diagnostic role of the model in identifying those algorithm components which restrict scaling performance. It is believed that the techniques presented may be useful both in developing embedded image coders based upon multiple DSP devices, and for simulation work with large image sequences in application areas such as image coding for HDTV and SHDTV.