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Resource-constrained system-on-a-chip test: a survey

Resource-constrained system-on-a-chip test: a survey

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Manufacturing test is a key step in the implementation flow of modern integrated electronic products. It certifies the product quality, accelerates yield learning and influences the final cost of the device. With the ongoing shift towards the core-based system-on-a-chip (SOC) design paradigm, unique test challenges, such as test access and test reuse, are confronted. In addition, when addressing these new challenges, the SOC designers must consciously use the resources at hand, while keeping the testing time and volume of test data under control. Consequently, numerous test strategies and algorithms in test architecture design and optimisation, test scheduling and test resource partitioning have emerged to tackle the resource-constrained core-based SOC test. This paper presents a survey of the recent advances in this field.

Inspec keywords: system-on-chip; production testing; logic testing

Other keywords: product quality; modern integrated electronic products; manufacturing test; test scheduling; test architecture optimization; test resource partitioning; test access; accelerated yield learning; resource-constrained system-on-a-chip test; core-based system-on-a-chip; testing time; test architecture design; test reuse

Subjects: Digital circuit design, modelling and testing; Production facilities and engineering; Logic design methods; Semiconductor integrated circuit design, layout, modelling and testing; Microprocessor chips; Microprocessors and microcomputers

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