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Dual basis systolic multipliers for GF(2m)

Dual basis systolic multipliers for GF(2m)

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Two systolic multipliers for GF(2m) are presented, one bit-serial and one bit-parallel. Both multipliers are hardware efficient and support pipelining. Both architectures are highly regular, require only local communication lines and have longest delay paths independent of m. Consequently these multipliers can be clocked at high speeds and are suitable for VLSI implementation. The design of both these multipliers is also independent of the defining irreducible polynomial for the field.

Inspec keywords: VLSI; error correction codes; multiplying circuits; Reed-Solomon codes; logic design

Other keywords: longest delay paths; local communication lines; irreducible polynomial; bit-serial; dual basis systolic multipliers; pipelining; VLSI implementation; GF(2m); bit-parallel

Subjects: Logic and switching circuits; Semiconductor integrated circuits; Logic circuits; Codes; Logic design methods

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