Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Application modelling and hardware description for network-on-chip benchmarking

Application modelling and hardware description for network-on-chip benchmarking

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

Measuring and comparing performance, cost and other features of advanced communication architectures for complex multicore/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This article presents a modelling concept for applications running on multicore systems and defines an extensible markup language (XML) format for documenting and distributing network-on-chip (NoC) benchmarks. It defines a black-box view of the processing elements that discloses only the computational aspects that are relevant in interacting with the on chip data transport mechanism. The purpose is to lay the groundwork for a standardised NoC benchmark set.

Inspec keywords: network-on-chip; multiprocessing systems; XML

Other keywords: extensible markup language; network-on-chip benchmarking; hardware description; multicore-multiprocessor system; on chip data transport mechanism; black-box view; XML format

Subjects: Microprocessors and microcomputers; Multimedia; Multiprocessing systems; Microprocessor chips

References

    1. 1)
      • Salminen, E., Kulmala, A., Hämäläinen, T.D.: `On network-on-chip comparisons', Proc. Euromicro Conf. Digital System Design, August 2007, Lübeck, Germany, p. 503–510.
    2. 2)
      • K. Holma , M. Setälä , E. Salminen , T.D. Hämäläinen . Evaluating the model accuracy in automated design space exploration. Microprocess. Microsyst. , 321 - 329
    3. 3)
      • Heirman , J. Dambre , J. van Campenhout . Synthetic traffic generation as a tool for dynamic interconnect evaluation. Proc. SLIP. , 65 - 72
    4. 4)
      • D. Stroobandt , P. Verplaetse , J. van Campenhout . Generating synthetic benchmark circuits for evaluating CAD tools. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 9 , 1011 - 1022
    5. 5)
      • Grecu, C., Ivanov, A., Saleh, R., Rusu, C., Anghel, L., Pande, P., Nuca, V.: `A flexible network-on-chip simulator for early design space exploration', IEEE Microsystems and Nanoelectronics Research Conf., October 2008, Ottawa, Canada, p. 33–36.
    6. 6)
      • T. Kangas . (2006) Methods and Implementations for Automated System on Chip Architecture Exploration.
    7. 7)
      • L. Benini , G. De Micheli . Networks on chips: a new SoC paradigm. IEEE Comput. , 1 , 70 - 78
    8. 8)
      • Kangas, T., Riihimäki, J., Salminen, E., Kuusilinna, K., Hämäläinen, T.D.: `Using a communication generator in SoC architecture exploration', Int. Symp. System-on-Chip, November 2003, Tampere, Finland, p. 105–108.
    9. 9)
      • C. Grecu , A. Ivanov , P.P. Pande . An Initiative towards open network-on-chip benchmarks.
    10. 10)
      • Holma, K., Arpinen, T., Salminen, E., Hännikäinen, M., Hämäläinen, T.D.: `Real-time execution monitoring on multi-processor system-on-chip', Int. Symp. System-on-Chip, November 2008, Tampere, Finland, p. 23–28.
    11. 11)
      • T. Bjerregaard , S. Mahadevan . A survey of research and practices of network-on-chip. ACM Comput. Surveys. , 1
    12. 12)
      • A.L. Sangiovanni-Vincentelli . Quo vadis SLD: Reasoning about trends and challenges of system-level design. Proc. IEEE , 3 , 467 - 506
    13. 13)
    14. 14)
      • W3C, Extensible markup language (XML), [online] http://www.w3.org/XML/.
    15. 15)
      • K.A. Goossens , J. Dielissen , O.P. Gangwal , S.G. Pestana , A. Radulescu , E. Rijpkema . A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. Proc DATE. , 1182 - 1187
    16. 16)
      • A. Weiss . (2002) Dhrystone benchmark – history, analysis, ‘scores’ and recommendations, White paper.
    17. 17)
      • A.D. Pimentel , M. Thompson , S. Polstra , C. Erbas . Calibration of abstract performance models for system-level design space exploration. J. VLSI Sig. Process. Syst. Signal Image Video Technol. , 2 , 99 - 114
    18. 18)
    19. 19)
      • Gustafson, J., Todi, R.: `Conventional benchmarks as a sample of the performance spectrum', Proc. HICSS, January 1998, Kohala Coast, HI, USA, 7, p. 514–523.
    20. 20)
      • R. Weicker . An overview of common benchmarks. IEEE Comput. , 12 , 65 - 75
    21. 21)
    22. 22)
      • Ogras, U.Y., Jingcao Hu, , Marculescu, R.: `Key research problems in NoC design: a holistic perspective', Proc. CODES, 2005, p. 69–75.
    23. 23)
      • A. Radulescu , J. Dielissen , S.G. Pestana . An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 1 , 4 - 17
    24. 24)
      • Bouchhima, A.: `Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration', Proc. ASP-DAC, 2005, 2, p. 969–972.
    25. 25)
      • W. Dally , B. Towles . Route packets, not wires: on-chip interconnection networks. Proc. DAC , 684 - 689
    26. 26)
      • J.D. Owens , W.J. Dally , R. Ho , D.N. Jayasimha , S.W. Keckler , L.-S. Peh . Research challenges for on-chip interconnection networks. IEEE Micro. , 5 , 96 - 108
    27. 27)
      • Salminen, E., Kulmala, A., Hämäläinen, T.D.: `Survey of network-on-chip proposals', White paper, OCP-IP, April 2008, p. 13.
    28. 28)
      • S. Mahadevan , F. Angiolini , M. Storgaard . A network traffic generator model for fast network-on-chip simulation. Proc. DATE. , 780 - 785
    29. 29)
      • P. Kukkala , M. Setälä , T. Arpinen . Implementing a WLAN video terminal using UML and fully-automated design flow. EURASIP J. Embedded Syst.
    30. 30)
      • SPIRIT Schema Working Group, SPIRIT-User guide v1.0, Dec. 2004, [online] http://www.spiritconsortium.org/.
    31. 31)
      • Leung, K., Yeung, K.: `The design and implementation of a WWW traffic generator', Proc. ICPADS, July 2000, p. 509–514.
    32. 32)
      • T. Kempf , M. Doerper , R. Leupers . A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms. Proc DATE. , 876 - 881
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2008.0065
Loading

Related content

content/journals/10.1049/iet-cdt.2008.0065
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address