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Experimental realisation of a full adder by substrate fed threshold logic structure

Experimental realisation of a full adder by substrate fed threshold logic structure

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© The Institution of Electrical Engineers
Published

A full adder has been designed and fabricated utilising substrate fed threshold logic. The internal operation is performed by four-valued threshold currents while the input and output signals are of binary form. The delay times of the experimental circuit operating with 10 μA per injection window have been measured as 5 μs for the sums and 1 μs for the carry.

Inspec keywords: adders; integrated logic circuits; many-valued logics; threshold logic

Other keywords: full adder; substrate fed threshold logic structure; binary form; delay times; four-valued threshold currents; logic ICs

Subjects: Logic and switching circuits; Logic circuits

References

    1. 1)
      • N. Friedman , C.A.T. Salama , F.E. Holmes , P.M. Thompson . Realization of a multivalued integrated injection logic (MVI2L) full adder. IEEE J. Solid-State Circuits , 532 - 534
    2. 2)
      • Johnson, C.A., Armstrong, J.R.: `Improved I', Proceedings of the 11th international symposium on multiple-valued logic, 1981, Oklahoma, p. 7–13.
    3. 3)
      • T.T. Dao . Threshold I2L and its applications to binary symmetric functions and multivalued logic. IEEE J. Solid-State Circuits , 463 - 472
    4. 4)
      • K.C. Smith . The prospects for multivalued logic: A technology and applications view. IEEE Trans. , 619 - 634
    5. 5)
      • C.H. Han , C.K. Kim , G.H. Yoo . Feasibility of substrate fed threshold logic. IEEE J. Solid-State Circuits
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