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Analysis for optimum threshold voltage and load current of E-D-type GaAs DCFL circuits

Analysis for optimum threshold voltage and load current of E-D-type GaAs DCFL circuits

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© The Institution of Electrical Engineers
Published

A GaAs MESFET E-D invertor was analysed to estimate the optimum threshold voltage VT for a switching FET, and the optimum load current IL for a load FET, that will minimise the invertor switching time. The calculated results show that the optimum VT lies at around 0.2 V, and the optimum IL is about 55% of the saturation current of the switching FET.

Inspec keywords: Schottky gate field effect transistors; invertors; gallium arsenide; field effect integrated circuits; integrated logic circuits; III-V semiconductors

Other keywords: optimum threshold voltage; load FET; optimum load current; logic circuit; E-D-type GaAs DCFL circuits; GaAs MESFET E-D invertor; switching FET; invertor switching time

Subjects: Logic circuits; Other field effect integrated circuits

References

    1. 1)
      • T. Mizutani , N. Kato , S. Ishida , K. Osafune , M. Ohmori . GaAs gigabit logic circuits using normally-off m.e.s.f.e.t.s. Electron. Lett. , 9 , 315 - 316
    2. 2)
      • W. Shockley . A unipolar “field-effect” transistor. Proc. IRE , 1365 - 1376
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