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C-element multiplexing for fault-tolerant logic circuits

C-element multiplexing for fault-tolerant logic circuits

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A novel approach to von Neumann multiplexing is considered, in which NAND gates are replaced by Muller C-elements. The new method is developed as an application of maximum a-posteriori (MAP) estimation, and is shown to be superior to NAND multiplexing in systems where transient upsets are the dominant fault species.

Inspec keywords: NAND circuits; algebra; maximum likelihood estimation; multiplying circuits

Other keywords: fault-tolerant logic circuits; NAND gates; transient upsets; NAND multiplexing; von Neumann multiplexing; Muller C-elements; C-element multiplexing; maximum a-posteriori estimation; dominant fault species

Subjects: Other topics in statistics; Logic and switching circuits; Logic circuits; Algebra; Other topics in statistics; Algebra

References

    1. 1)
      • Jang, W., Martin, A.J.: `Soft-error robustness in QDI circuits', Proc. 1st Workshop on System Effects of Logic Soft Errors, April 2005.
    2. 2)
      • V.C. Gaudet , A. Rapley . Iterative decoding using stochastic computation. Electron. Lett. , 3 , 299 - 301
    3. 3)
      • K. Nikolic , A. Sadek , M. Forshaw . Fault-tolerant techniques for nanocomputers. Nanotechnology , 3 , 357 - 362
    4. 4)
      • Muller, D.E., Bertky, W.S.: `A theory of asynchronous circuits', Proc. Int. Symp. on the Theory of Switching, Part 1, 1959, p. 204–243.
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