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Minimum current/area implementation of cyclic ADC

Minimum current/area implementation of cyclic ADC

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Published

A global offset cancellation technique is proposed to solve the offset/flicker noise problem. It helps to minimise the silicon area and power consumption of a cyclic analogue-to-digital converter (ADC) with an operational transconductance amplifier sharing scheme. A 10 bit 1 MS/s cyclic ADC implemented in the TI 0.35 µm CMOS process proves the effectiveness of the proposed technique.

Inspec keywords: CMOS analogue integrated circuits; flicker noise; operational amplifiers; analogue-digital conversion

Other keywords: offset-flicker noise problem; global offset cancellation technique; operational transconductance amplifier; size 0.35 mum; cyclic ADC; cyclic analogue-to-digital converter; CMOS process

Subjects: Other topics in statistics; Other topics in statistics; A/D and D/A convertors; A/D and D/A convertors; Amplifiers; CMOS integrated circuits

References

    1. 1)
      • Picolli, L., Maloberti, F., Rossini, A., Borghetti, F., Malcovati, P., Baschirotto, A.: `A 10-bit pipeline A/D converter without timing signals', Proc. 2006 IEEE Int. Symp. on Circuits and Systems, May 2006, 1, p. 5355–5358.
    2. 2)
    3. 3)
      • S.H. Lewis , H.S. Fetterman , G.F. Gross , R. Ramachandran , T.R. Viswanathan . A 10-b 20MS/s analog-to-digital converter. IEEE J. Solid-State Circuits , 3 , 351 - 358
    4. 4)
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2009.0293
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