Abstract
Two-dimensional semiconductors such as layered transition metal dichalcogenides can offer superior immunity to short-channel effects compared with bulk semiconductors such as silicon. As a result, these materials can be used to create highly scaled transistors. However, on-state current densities of two-dimensional semiconductor transistors are still below those of silicon transistors. Here we show that bilayer tungsten diselenide transistors that have channel lengths of less than 100 nm can exhibit on-state current densities above 1.0 mA μm−1 and on-state resistances below 1.0 kΩ μm at room temperature. The devices have atomically clean van der Waals vanadium diselenide contacts and are created using van der Waals epitaxy and controlled crack formation processes. With a 20-nm-long and 1.3-nm-thick transistor, an on-state current density of 1.72 mA μm−1 and on-state resistance of 0.50 kΩ μm are achieved, showing comparable performance to silicon transistors with similar channel lengths and driving voltages.
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Data availability
The data that support the findings of this study are available from the corresponding author upon reasonable request.
Change history
14 November 2022
A Correction to this paper has been published: https://doi.org/10.1038/s41928-022-00891-y
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Acknowledgements
The authors at Hunan University acknowledge support from the National Key Research and Development Program of China (grant no. 2018YFE0202700), National Natural Science Foundation of China (nos. 51802090, 51872086, 51991343, 51991341, 51991340 and 61874041), the Hunan Key Laboratory of Two-Dimensional Materials (grant no. 2018TP1010) and the Innovative Research Groups of Hunan Province (grant no. 2020JJ1001).
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Xidong Duan conceived the research. R.W. developed a lithography-free approach to sub-100-nm channel lengths and measured all the devices. Q.T., W.L., Y.C., Z.S., H.D. and L.L. performed the device fabrication. J.L. participated in the investigation of the crack formation mechanism. J.L., H.M. and B.Z. participated in materials growth as well as TEM and HAADF-STEM characterizations. R.W., Q.T., Z.Z., X.Y., B.L. and Y.L. contributed to the discussions and data analysis. Xidong Duan supervised the research. R.W., Xidong Duan and Xiangfeng Duan co-wrote the manuscript with inputs from all the authors. All the authors discussed the results and commented on the manuscript.
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Extended data
Extended Data Fig. 1 The Raman and PL spectrum of the VSe2/WSe2.
a, b Raman spectrum and PL spectrum obtained from the measurement area on both sides of the crack of VSe2/WSe2, respectively.
Extended Data Fig. 2 Electron microscopy characterizations of the sub-100 nm bilayer WSe2 transistors.
a, The SAED pattern of the bare WSe2. b, The SAED pattern collected from the overlapping VSe2/WSe2 region shows two sets of electron diffraction patterns, corresponding to WSe2 and VSe2, respectively. The insets in (a, b) show a magnified view of a selected area electron diffraction spot. The diffraction spots from the overlapping VSe2/WSe2 area shows two sets of identically orientated diffraction spots with the inner and outer set corresponding to the 1T-VSe2 and 2H-WSe2. (c) HAADF-STEM image taken on the bare WSe2 region with a lattice constant of 3.29 Å for of WSe2. (d) HAADF-STEM image taken on the VSe2 region show a lattice constant of 3.36 Å for VSe2. Scale bars: a, b 2 nm−1; c, d 2 nm.
Extended Data Fig. 3 Energy dispersive spectroscopy (EDS) elemental mapping image.
The distribution of the entire element mapping image of the cross-sectional image of (VSe2/WSe2)–WSe2–(VSe2/WSe2) device supported on the 70 nm SiNx substrate. Scale bar: 20 nm.
Extended Data Fig. 4 Electrical characterizations of 10 sub-100 nm WSe2 devices.
a1 - j2, The output and transfer curves of 10 sub-100 nm WSe2 devices at room temperature. The Vgs varies with a 5 V step in the output curves.
Extended Data Fig. 5 Electrical characteristics of the sub-100 nm monolayer WSe2 transistors.
a, Output characteristics of the 72-nm-length monolayer WSe2 transistors at various back-gate voltages with a step of 5 V. The inset shows the SEM image of the monolayer WSe2 transistor with 72 nm channel length. Scale bars: 100 nm. b, Transfer curves of the 72-nm-length monolayer WSe2 transistor at various bias voltages.
Extended Data Fig. 6 Top-gated ultra-short channel bilayer WSe2 transistor.
a, SEM image of the top-gated bilayer WSe2 transistor with ~3 nm Al2O3/6 nm HfO2 as top-gate dielectrics. The length and width of the WSe2 transistor are 80 nm and 6.0 μm. The scale of inset is 5 μm. b, Transfer curves of the 80-nm-length transistor at various bias voltages when Vbg is fixed at −30 V. c, Output characteristics of the 80-nm-length WSe2 transistor at various top-gate voltages with a step of 1 V.
Extended Data Fig. 7 Ultrashort WSe2 channel array with VSe2 contacts generated by synthesis of WSe2/VSe2 vdW heterostructure array and following controlled crack formation process.
a, The OM images of 1 × 6 ultrashort channels of WSe2 array with VSe2 synthetic contacts. b-f, The corresponding SEM images of a. Scale bars: 1 μm.
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Wu, R., Tao, Q., Li, J. et al. Bilayer tungsten diselenide transistors with on-state currents exceeding 1.5 milliamperes per micrometre. Nat Electron 5, 497–504 (2022). https://doi.org/10.1038/s41928-022-00800-3
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DOI: https://doi.org/10.1038/s41928-022-00800-3
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