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Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems

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Abstract

The purpose of this paper is to present a novel methodology for Defect-Oriented (DO) fault sampling, and its implementation in a new extraction tool, lobs (\((\underset{\raise0.3em\hbox{$\smash{\scriptscriptstyle-}$}}{L} ayout \underline {Obs} erver)\)). The methodology is based on the statistics theory, and on the application of the concepts of estimation of totals over subpopulations and stratified sampling to the fault sampling problem. The proposed stratified sampling methodology applies to non-equally probable DO faults, exhibiting a wide range of probabilities of occurrence, and leads to confidence intervals similar to the ones obtained with equally probable faults. ISCAS benchmark circuits are laid out and lobs used to ascertain the results, for circuits up to 100,000 MOS transistors, and extracted DO fault lists of 300,000 faults.

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  1. IST/INESC, Apartado 13069, 1017, Lisboa Codex, Portugal

    F.M. Gonçalves & J.P. Teixeira

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  1. F.M. Gonçalves
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  2. J.P. Teixeira
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Gonçalves, F., Teixeira, J. Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems. Journal of Electronic Testing 15, 41–52 (1999). https://doi.org/10.1023/A:1008351310657

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