Abstract
Modern processors embed features such as pipelined execution units and cache memories that can not be directly controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are even less suitable for assessing the effects of SEUs in modern processors, since they are not able to evaluate the effects of SEUs affecting pipelines and caches. In this paper we report an analysis of a commercial processor core where the effects of SEUs located in the processor pipeline and cache memories are studied. The obtained results are compared with those software-based approaches provide, showing that software-based approaches may lead to significant errors during the error rate estimation. A major novelty of the paper is an extensive analysis of the effects of SEUs in the pipeline of a commercial processor core during the execution of several benchmark programs.
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Rebaudengo, M., Reorda, M.S. & Violante, M. Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. Journal of Electronic Testing 19, 577–584 (2003). https://doi.org/10.1023/A:1025130131636
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DOI: https://doi.org/10.1023/A:1025130131636