Abstract
Several useful compiler and program transformation techniques for the superthreaded architectures are presented in this paper. The superthreaded architecture adopts a thread pipelining execution model to facilitate runtime data dependence checking between threads, and to maximize thread overlap to enhance concurrency. In this paper, we present some important program transformation techniques to facilitate concurrent execution among threads, and to manage critical system resources such as the memory buffers effectively. We evaluate the effectiveness of those program transformation techniques by applying them manually on several benchmark programs, and using a trace-driven, cycle-by-cycle superthreaded processor simulator. The simulation results show that a superthreaded processor can achieve promising speedup for most of the benchmark programs.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
REFERENCES
Jenn-Yuan Tsai and Pen-Chung Yew, The Superthreaded Architecture: Thread Pipelining with Runtime Data Dependence Checking and Control Speculation, Proc. Conf. Parallel Architectures and Compilation Techniques 96, pp. 35–46 (October 20– 23, 1996).
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yoshiyuki Mochizuki, Akio Nishimura, Yoshimori Nakase, and Teiji Nishizawa, An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads, Proc. 19th Ann. Int' l Symp. Computer Architecture, pp. 136–145 (May 19– 21, 1992).
Gurindar S. Sohi, Scott E. Breach, and T. N. Vijaykumar, Multiscalar Processors, Proc. 22nd Ann. Int'l Symp. Computer Architecture, pp. 414–425 (June 22– 24, 1995).
Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy, Simultaneous Multithreading:Maximizing On-Chip Parallelism, Proc. 22nd Ann. Int'l Symp. Computer Architecture, pp. 392–403 (June 22– 24, 1995).
Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, and Whay S. Lee, The m-Machine Multicomputer, Proc. 28th Ann. Int' l Symp. Microarchitecture, pp. 146–156 (November 29– December 1, 1995).
Pradeep K. Dubey, Kevin O'Brien, Kathryn O'Brien, and Charles Barton, Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading, Proc. IFIP WG 10.3 Working Conf. Parallel Architectures and Compilation Techniques PACT '95, pp. 109–121 (June 27–29, 1995).
Ding-Kai Chen and Pen-Chung Yew, Statement Reordering for Doacross Loops, Proc. Int'l Conf. Parallel Processing, Vol. II, pp. 24–28 (August 1994).
Manoj Franklin and Gurindar S. Sohi, The Expandable Split Window Paradigm for Exploiting Fine-Grained Parallelism, Proc. 19th Ann. Int'l Symp. Computer Architecture, pp. 58–67 (May 19– 21, 1992).
M. D. Smith, Tracing with Pixie. Technical Report, Stanford University, Stanford, California 94305, Technical Report CSL-TR-pp 91–497 (November 1991).
Rights and permissions
About this article
Cite this article
Tsai, JY., Jiang, Z. & Yew, PC. Compiler Techniques for the Superthreaded Architectures1, 2 . International Journal of Parallel Programming 27, 1–19 (1999). https://doi.org/10.1023/A:1018730501763
Issue Date:
DOI: https://doi.org/10.1023/A:1018730501763