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On-Chip Clock Faults' Detector

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Abstract

This paper proposes an on-chip detector for the on-line testing of faults affecting clock signals and making them change with incorrect duty-cycle. Our scheme is particularly suitable to be integrated within Systems-On-a-Chip (SOCs), in order to avoid their possible incorrect operation because of faults affecting clock signals, thus solving their extreme criticality in clock faults' testing. In particular, our detector is suitable to be applied to clock signals within each SOC digital core, to the clock signals at the interface between the diverse cores, as well as to those driving the DFT and BIST structures used to perform the SOC test. Our scheme features self-checking ability with respect to its possible internal faults belonging to a realistic set including stuck-ats, transistor stuck-ons, stuck-opens and resistive bridgings.

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Authors and Affiliations

  1. DEIS—, University of Bologna, Viale Risorgimento 2, 40136, Bologna, Italy

    C. Metra

  2. DI—, University of Ferrara, Viale Saragat 1, 44100, Ferrara, Italy

    M. Favalli

  3. DEIS—, University of Bologna, Viale Risorgimento 2, 40136, Bologna, Italy

    S. Di Francescantonio & B. Riccò

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  1. C. Metra
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  3. S. Di Francescantonio
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  4. B. Riccò
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Metra, C., Favalli, M., Di Francescantonio, S. et al. On-Chip Clock Faults' Detector. Journal of Electronic Testing 18, 555–564 (2002). https://doi.org/10.1023/A:1016570230205

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