Abstract
The cost-effective testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, costly testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a Design for Delay Testability (DfDT) technique such that high-speed ICs can be tested using inexpensive, low-speed test systems. Also extensions for possible full BIST of delay faults are addressed.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
V.D. Agrawal and T. J. Chakraborty, “High-Performance Circuit Testing with Slow-Speed Testers,” in Proc. International Test Conf., 1995, pp. 302-310.
K. Arabi, H. Ihs, C. Dufaza, and B. Kaminska, “Digital Oscillation-Test Method for Delay and Stuck-at Fault Testing of Digital Circuits,” in Proc. International Test Conf., 1998, pp. 91-100.
C. Dufaza and Y. Zorian, “On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LSFRs,” in Proc. European Design & Test Conf., France, 1997, pp. 69-76.
P. Girard, “An Optimized BIST Test-Pattern Generator for Delay Testing,” in Proc. IEEE VLSI Test Symp., 1997, pp. 94-100.
A. Keshavarzi, K. Roy, and C.F. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs,” in Proc. International Test Conf., 1997, pp. 146-155.
G.C. Moyer et al., “The Delay Vernier Pattern Generation Technique,” IEEE Jrnl. of Solid-State Circuits, Vol. 32,No. 4, pp. 551-562, April 1997.
N. Mukherjee, T.J. Chakraborty, S. Bhawmik, “A BIST Scheme for the Detection of Path-Delay Faults,” in Proc. International Test Conf., 1998, pp. 422-431.
P. Nigh, W. Needham, K. Butler, P. Maxwell, R. Aitken, and W. Maly, “So What is an Optimal Test Mix? A Discussion of Test Sematech Methods Experiment,” in Proc. International Test Conf., 1997, pp. 1037-1038.
Roadmap for Semiconductors, Semiconductor Industry Association (SIA), 1997.
J. Savir, “Scan Latch Design for Delay Test,” in Proc. International Test Conf., 1997, pp. 446-453.
M. Shashaani and M. Sachdev, “A Df T Technique for High Performance Circuit Testing,” in Proc. of International Test Conf., 1999, pp. 276-285.
G. Singer, “The Future of Test and Df T,” IEEE Design & Test of Computers, Vol. 14,No. 3, pp. 11-14, July–September 1997.
H. Speek, M. Shashaani, M. Sachdev, and H.G. Kerkhoff, “A Low-Speed BIST Framework for High-Performance Circuit Testing,” in Proc. IEEE VLSI Test Symp., Montreal, Canada, April 2000, pp. 349-355.
K.D. Wagner and E. McCluskey, “Effect of Supply Voltage on Circuit Propagation Delay and Test Application,” in Proc. International Conf. Computer-Aided Design, 1985, pp. 42-44.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Kerkhoff, H., Speek, H., Shashani, M. et al. Design for Delay Testability in High-Speed Digital ICs. Journal of Electronic Testing 17, 225–231 (2001). https://doi.org/10.1023/A:1012207210784
Issue Date:
DOI: https://doi.org/10.1023/A:1012207210784