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New Techniques for Deterministic Test Pattern Generation

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Abstract

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an advanced ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance. ATOM detected all the testable faults and proved all the redundant faults to be redundant with a small number of backtracks in a short amount of time.

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Authors and Affiliations

  1. enter for Reliable & High-Performance Computing, University of Illinois, Urbana, IL, 61801, USA

    Ilker Hamzaoglu & Janak H. Patel

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  1. Ilker Hamzaoglu
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  2. Janak H. Patel
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Hamzaoglu, I., Patel, J.H. New Techniques for Deterministic Test Pattern Generation. Journal of Electronic Testing 15, 63–73 (1999). https://doi.org/10.1023/A:1008355411566

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  • DOI: https://doi.org/10.1023/A:1008355411566

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